PIC18F97J60_11 Datasheet, PDF (257/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
19.7 Flow Control
The Ethernet module implements hardware flow con-
trol for both Full and Half-Duplex modes. The operation
of this feature differs depending on which mode is
being used.
19.7.1 HALF-DUPLEX MODE
In Half-Duplex mode, setting the FCEN0 bit
(EFLOCON<0>) causes flow control to be enabled.
When FCEN0 is set, a continuous preamble pattern of
alternating ‘1’s and ‘0’s (55h) will automatically be
transmitted on the Ethernet medium. Any connected
nodes will see the transmission and either not transmit
anything, waiting for the transmission to end, or will
attempt to transmit and immediately cause a collision.
Because a collision will always occur, no nodes on the
network will be able to communicate with each other
and no new packets will arrive.
When the application causes the module to transmit a
packet by setting the TXRTS bit, the preamble pattern
will stop being transmitted. An inter-packet delay will
pass as configured by register, MABBIPG, and then the
module will attempt to transmit its packet. After the
inter-packet delay, other nodes may begin to transmit.
Because all traffic was jammed previously, several
nodes may begin transmitting and a series of collisions
may occur. When the module successfully finishes
transmitting its packet or aborts it, the transmission of
the preamble pattern will automatically restart. When
the application wishes to no longer jam the network, it
should clear the FCEN0 bit. The preamble transmis-
sion will cease and normal network operation will
resume.
Given the detrimental network effects that are possible
and lack of effectiveness, it is not recommended that
half-duplex flow control be used unless the application
will be in a closed network environment with proper
testing.
19.7.2 FULL-DUPLEX MODE
In Full-Duplex mode (MACON3<0> = 1), hardware flow
control is implemented by means of transmitting pause
control frames, as defined by the IEEE 802.3 specifica-
tion. Pause control frames are 64-byte frames consisting
of the reserved Multicast destination address of
01-80-C2-00-00-01, the source address of the sender, a
special pause opcode, a 2-byte pause timer value and
padding/CRC.
Normally, when a pause control frame is received by a
MAC, the MAC will finish the packet it is transmitting
and then stop transmitting any new frames. The pause
timer value will be extracted from the control frame and
used to initialize an internal timer. The timer will auto-
matically decrement every 512 bit times, or 51.2 s.
While the timer is counting down, reception of packets
is still enabled. If new pause frames arrive, the timer will
be re-initialized with the new pause timer value. When
the timer reaches zero, or was sent a frame with a zero
pause timer value, the MAC that received the pause
frame will resume transmitting any pending packets. To
prevent a pause frame from stopping all traffic on the
entire network, Ethernet switches and routers do not
propagate pause control frames in Full-Duplex mode.
The pause operation only applies to the direct recipient.
A sample network is shown in Figure 19-12. If
Computer A were to be transmitting too much data to
the microcontroller-based application in Full-Duplex
mode, the Ethernet module could transmit a pause
control frame to stop the data which is being sent to it.
The Ethernet switch would take the pause frame and
stop sending data to the application. If Computer A
continues to send data, the Ethernet switch will buffer
the data so it can be transmitted later when its pause
timer expires. If the Ethernet switch begins to run out of
buffer space, it will likely transmit a pause control frame
of its own to Computer A.
If, for some reason the Ethernet switch does not gener-
ate a pause control frame of its own, or one of the
nodes does not properly handle the pause frame it
receives, then packets will inevitably be dropped. In
any event, any communication between Computer A
and Computer B will always be completely unaffected.
FIGURE 19-12:
SAMPLE FULL-DUPLEX
NETWORK
 2011 Microchip Technology Inc.
DS39762F-page 257