PIC18F97J60_11 Datasheet, PDF (245/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

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19.4 Module Initialization
Before the Ethernet module can be used to transmit
and receive packets, certain device settings must be
initialized. Depending on the application, some config-
uration options may need to be changed. Normally,
these tasks may be accomplished once after Reset and
do not need to be changed thereafter.
Before any other configuration actions are taken, it is
recommended that the module be enabled by setting
the ETHEN bit (ECON2<5>). This reduces the Idle time
that might otherwise result while waiting for the
PHYRDY flag to become set.
19.4.1 RECEIVE BUFFER
Before receiving any packets, the receive buffer must
be initialized by setting the ERXST and ERXND Point-
ers. All memory between and including the ERXST and
ERXND addresses will be dedicated to the receive
hardware. The ERXST Pointers must be programmed
with an even address while the ERXND Pointers must
be programmed with an odd address.
Applications expecting large amounts of data and
frequent packet delivery may wish to allocate most of
the memory as the receive buffer. Applications that
may need to save older packets, or have several
packets ready for transmission, should allocate less
memory.
When programming the ERXST or ERXND Pointers, the
ERXWRPT Pointer registers will automatically be
updated with the value in the ERXST registers. The
address in the ERXWRPT registers will be used as the
starting location when the receive hardware begins
writing received data. When the ERXST and ERXND
Pointers are initialized, the ERXRDPT registers should
additionally be programmed with the value of the
ERXND registers. To program the ERXRDPT registers,
write to ERXRDPTL first, followed by ERXRDPTH. See
Section 19.5.3.3 “Freeing Receive Buffer Space” for
more information.
19.4.2 TRANSMISSION BUFFER
All memory which is not used by the receive buffer is
considered to be the transmission buffer. Data which is
to be transmitted should be written into any unused
space. After a packet is transmitted, however, the hard-
ware will write a 7-byte status vector into memory after
the last byte in the packet. Therefore, the application
should leave at least 7 bytes between each packet and
the beginning of the receive buffer.
19.4.3 RECEIVE FILTERS
The appropriate receive filters should be enabled or
disabled by writing to the ERXFCON register. See
Section 19.8 “Receive Filters” for information on how
to configure it.
19.4.4
WAITING FOR THE PHY START-UP
TIMER
If the initialization procedure is being executed immedi-
ately after enabling the module (setting the ETHEN bit
to ‘1’), the PHYRDY bit should be polled to make
certain that enough time (1 ms) has elapsed before
proceeding to modify the PHY registers. For more
information on the PHY start-up timer, see
Section 19.1.3.1 “Start-up Timer”.
19.4.5 MAC INITIALIZATION SETTINGS
Several of the MAC registers require configuration during
initialization. This only needs to be done once during
initialization; the order of programming is unimportant.
1. Set the MARXEN bit (MACON1<0>) to enable
the MAC to receive frames. If using full duplex,
most applications should also set TXPAUS and
RXPAUS to allow IEEE defined flow control to
function.
2. Configure the PADCFG<2:0>, TXCRCEN and
FULDPX bits in the MACON3 register. Most
applications should enable automatic padding to
at least 60 bytes and always append a valid
CRC. For convenience, many applications may
wish to set the FRMLNEN bit as well to enable
frame length status reporting. The FULDPX bit
should be set if the application will be connected
to a full-duplex configured remote node;
otherwise leave it clear.
3. Configure the bits in MACON4. For maintaining
compliance with IEEE 802.3, be certain to set
the DEFER bit (MACON4<6>).
4. Program the MAMXFL registers with the maxi-
mum frame length to be permitted to be received
or transmitted. Normal network nodes are
designed to handle packets that are 1518 bytes
or less; larger packets are not supported by
IEEE 802.3.
5. Configure the MAC Back-to-Back Inter-Packet
Gap register, MABBIPG, with 15h (when
Full-Duplex mode is used) or 12h (when
Half-Duplex mode is used). Refer to
Register 19-18 for a more detailed description of
configuring the inter-packet gap.
6. Configure the MAC Non Back-to-Back
Inter-Packet Gap Low Byte register, MAIPGL,
with 12h.
7. If half duplex is used, configure the MAC Non
Back-to-Back Inter-Packet Gap High Byte
register, MAIPGH, with 0Ch.
8. Program the local MAC address into the
MAADR1:MAADR6 registers.
 2011 Microchip Technology Inc.
DS39762F-page 245