PIC18F97J60_11 Datasheet, PDF (294/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
20.4.4.5 Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCLx output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCLx output low until the SCLx output is already
sampled low. Therefore, the CKP bit will not assert the
SCLx line until an external I²C master device has
already asserted the SCLx line. The SCLx output will
remain low until the CKP bit is set and all other
devices on the I²C bus have deasserted SCLx. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCLx (see
Figure 20-14).
FIGURE 20-14: CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDAx
SCLx
CKP
WR
SSPxCON1
DX
Master device
asserts clock
Master device
deasserts clock
DX – 1
DS39762F-page 294
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