PIC18F97J60_11 Datasheet, PDF (173/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
12.3 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module. The prescaler is not directly readable
or writable. Its value is set by the PSA and T0PS<2:0>
bits (T0CON<3:0>) which determine the prescaler
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256, in power-of-2 increments, are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
12.3.1
SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
12.4 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before
re-enabling the interrupt, the TMR0IF bit must be
cleared in software by the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
TMR0L
Timer0 Register Low Byte
TMR0H Timer0 Register High Byte
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF
INTCON2
RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
T0CON
TMR0ON T08BIT T0CS
T0SE
PSA
T0PS2
TRISA
—
—
TRISA5 TRISA4 TRISA3 TRISA2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.
Bit 1
INT0IF
INT3IP
T0PS1
TRISA1
Bit 0
RBIF
RBIP
T0PS0
TRISA0
Reset
Values
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 2011 Microchip Technology Inc.
DS39762F-page 173