PIC18F97J60_11 Datasheet, PDF (39/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number _{Pin Buffer}
TQFP
Type Type
Description
RG0/ECCP3/P3A
RG0
ECCP3
P3A
PORTG is a bidirectional I/O port.
71
I/O
ST
Digital I/O.
I/O
ST
Capture 3 input/Compare 3 output/PWM3 output.
O
—
ECCP3 PWM Output A.
RG1/TX2/CK2
RG1
TX2
CK2
70
I/O
ST
Digital I/O.
O
—
EUSART2 asynchronous transmit.
I/O
ST
EUSART2 synchronous clock (see related RX2/DT2 pin).
RG2/RX2/DT2
RG2
RX2
DT2
52
I/O
ST
Digital I/O.
I
ST
EUSART2 asynchronous receive.
I/O
ST
EUSART2 synchronous data (see related TX2/CK2 pin).
RG3/CCP4/P3D
RG3
CCP4
P3D
51
I/O
ST
Digital I/O.
I/O
ST
Capture 4 input/Compare 4 output/PWM4 output.
O
—
ECCP3 PWM Output D.
RG4/CCP5/P1D
RG4
CCP5
P1D
14
I/O
ST
Digital I/O.
I/O
ST
Capture 5 input/Compare 5 output/PWM5 output.
O
—
ECCP1 PWM Output D.
RG5
11
I/O
ST
Digital I/O.
RG6
10
I/O
ST
Digital I/O.
RG7
Legend:
Note 1:
2:
3:
4:
5:
38
I/O
ST
Digital I/O.
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
OD
= Open-Drain (no P diode to VDD)
Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
 2011 Microchip Technology Inc.
DS39762F-page 39