PIC18F97J60_11 Datasheet, PDF (167/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 11-19: PORTJ FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RJ0/ALE⁽¹⁾
RJ0⁽¹⁾
0
1
ALE⁽¹⁾
x
RJ1/OE⁽¹⁾
RJ1⁽¹⁾
0
1
OE⁽¹⁾
x
RJ2/WRL⁽¹⁾
RJ2⁽¹⁾
0
1
WRL⁽¹⁾
x
RJ3/WRH⁽¹⁾
RJ3⁽¹⁾
0
1
WRH⁽¹⁾
x
RJ4/BA0
RJ4
0
1
BA0⁽²⁾
x
O
DIG LATJ<0> data output.
I
ST PORTJ<0> data input; weak pull-up when RJPU bit is set.
O
DIG External memory interface address latch enable control output; takes
priority over digital I/O.
O
DIG LATJ<1> data output.
I
ST PORTJ<1> data input; weak pull-up when RJPU bit is set.
O
DIG External memory interface output enable control output; takes priority
over digital I/O.
O
DIG LATJ<2> data output.
I
ST PORTJ<2> data input; weak pull-up when RJPU bit is set.
O
DIG External memory bus write low byte control; takes priority over
digital I/O.
O
DIG LATJ<3> data output.
I
ST PORTJ<3> data input; weak pull-up when RJPU bit is set.
O
DIG External memory interface write high byte control output; takes priority
over digital I/O.
O
DIG LATJ<4> data output.
I
ST PORTJ<4> data input; weak pull-up when RJPU bit is set.
O
DIG External Memory Interface Byte Address 0 control output; takes
priority over digital I/O.
RJ5/CE
RJ5
0
O
DIG LATJ<5> data output.
1
I
ST PORTJ<5> data input; weak pull-up when RJPU bit is set.
CE⁽²⁾
x
O
DIG External memory interface chip enable control output; takes priority
over digital I/O.
RJ6/LB⁽¹⁾
RJ6⁽¹⁾
0
O
DIG LATJ<6> data output.
1
I
ST PORTJ<6> data input; weak pull-up when RJPU bit is set.
LB⁽¹⁾
x
O
DIG External memory interface lower byte enable control output; takes
priority over digital I/O.
RJ7/UB⁽¹⁾
RJ7⁽¹⁾
0
O
DIG LATJ<7> data output.
1
I
ST PORTJ<7> data input; weak pull-up when RJPU bit is set.
UB⁽¹⁾
x
O
DIG External memory interface upper byte enable control output; takes
priority over digital I/O.
Legend:
Note 1:
2:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Implemented on 100-pin devices only.
EMB functions are implemented on 100-pin devices only.
TABLE 11-20: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTJ
LATJ
TRISJ
PORTA
Legend:
Note 1:
RJ7⁽¹⁾
RJ6⁽¹⁾
RJ5
RJ4
RJ3⁽¹⁾
RJ2⁽¹⁾
RJ1⁽¹⁾
LATJ7⁽¹⁾ LATJ6⁽¹⁾ LATJ5
LATJ4 LATJ3⁽¹⁾ LATJ2⁽¹⁾ LATJ1⁽¹⁾
TRISJ7⁽¹⁾ TRISJ6⁽¹⁾ TRISJ5 TRISJ4 TRISJ3⁽¹⁾ TRISJ2⁽¹⁾ TRISJ1⁽¹⁾
RJPU
—
RA5
RA4
RA3
RA2
RA1
— = unimplemented, read as ‘0’. Shaded cells are not used by PORTJ.
Implemented on 100-pin devices only.
RJ0⁽¹⁾
LATJ0⁽¹⁾
TRISJ0⁽¹⁾
RA0
Reset
Values
on Page:
72
71
71
72
 2011 Microchip Technology Inc.
DS39762F-page 167