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PIC18F97J60_11 Datasheet, PDF (412/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet | |||
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PIC18F97J60 FAMILY
SUBWFB
Subtract W from f with Borrow
Syntax:
SUBWFB f {,d {,a}}
Operands:
0 ï£ f ï£ 255
d ï [0,1]
a ï [0,1]
Operation:
(f) â (W) â (C) ï®ï dest
Status Affected: N, OV, C, DC, Z
Encoding:
Description:
0101 10da ffff ffff
Subtract W and the Carry flag (borrow)
from register âfâ (2âs complement
method). If âdâ is â0â, the result is stored
in W. If âdâ is â1â, the result is stored back
in register âfâ (default).
If âaâ is â0â, the Access Bank is selected.
If âaâ is â1â, the BSR is used to select the
GPR bank (default).
Words:
If âaâ is â0â and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ï£ï 95 (5Fh). See
Section 26.2.3 âByte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Modeâ for details.
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Example 1:
SUBWFB
Before Instruction
REG
W
C
= 19h
= 0Dh
=1
After Instruction
REG
W
C
Z
N
= 0Ch
= 0Dh
=1
=0
=0
Example 2:
SUBWFB
Before Instruction
REG
W
C
= 1Bh
= 1Ah
=0
After Instruction
REG
W
C
Z
N
= 1Bh
= 00h
=1
=1
=0
Example 3:
SUBWFB
Before Instruction
REG
W
C
= 03h
= 0Eh
=1
After Instruction
REG = F5h
W
= 0Eh
C
=0
Z
=0
N
=1
REG, 1, 0
(0001 1001)
(0000 1101)
(0000 1011)
(0000 1101)
; result is positive
REG, 0, 0
(0001 1011)
(0001 1010)
(0001 1011)
; result is zero
REG, 1, 0
(0000 0011)
(0000 1101)
(1111 0100)
; [2âs comp]
(0000 1101)
; result is negative
SWAPF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Swap f
SWAPF f {,d {,a}}
0 ï£ f ï£ 255
d ï [0,1]
a ï [0,1]
(f<3:0>) ï® dest<7:4>,
(f<7:4>) ï® dest<3:0>
None
0011 10da ffff ffff
The upper and lower nibbles of register
âfâ are exchanged. If âdâ is â0â, the result
is placed in W. If âdâ is â1â, the result is
placed in register âfâ (default).
If âaâ is â0â, the Access Bank is selected.
If âaâ is â1â, the BSR is used to select the
GPR bank (default).
If âaâ is â0â and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ï£ï 95 (5Fh). See
Section 26.2.3 âByte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Modeâ for details.
1
1
Q2
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Example:
SWAPF
Before Instruction
REG = 53h
After Instruction
REG = 35h
REG, 1, 0
DS39762F-page 412
ï£ 2011 Microchip Technology Inc.
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