PIC18F97J60_11 Datasheet, PDF (142/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
SSP2IP⁽¹⁾
bit 7
R/W-1
BCL2IP⁽¹⁾
R/W-1
RC2IP⁽²⁾
R/W-1
TX2IP⁽²⁾
R/W-1
TMR4IP
R/W-1
CCP5IP
R/W-1
CCP4IP
R/W-1
CCP3IP
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SSP2IP: MSSP2 Interrupt Priority bit⁽¹⁾
1 = High priority
0 = Low priority
bit 6
BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module)⁽¹⁾
1 = High priority
0 = Low priority
bit 5
RC2IP: EUSART2 Receive Interrupt Priority bit⁽²⁾
1 = High priority
0 = Low priority
bit 4
TX2IP: EUSART2 Transmit Interrupt Priority bit⁽²⁾
1 = High priority
0 = Low priority
bit 3
TMR4IE: TMR4 to PR4 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
CCP5IP: CCP5 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
CCP4IP: CCP4 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
CCP3IP: ECCP3 Interrupt Priority bit
1 = High priority
0 = Low priority
Note 1: Implemented in 100-pin devices only.
2: Implemented in 80-pin and 100-pin devices only.
DS39762F-page 142
 2011 Microchip Technology Inc.