PIC18F97J60_11 Datasheet, PDF (267/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
19.10 Module Resets
The Ethernet module provides selective module
Resets:
• Transmit Only Reset
• Receive Only Reset
19.10.1 MICROCONTROLLER RESETS
Following any standard Reset event, the Ethernet
module returns to a known state. The contents of the
Ethernet buffer memory are unknown. All SFR and
PHY registers are loaded with their specified Reset val-
ues, depending on the type of Reset event. However,
the PHY registers must not be accessed until the PHY
start-up timer has expired and the PHYRDY bit
(ESTAT<0>) becomes set, or at least 1 ms has passed
since the ETHEN bit was set. For more details, see
Section 19.1.3.1 “Start-up Timer”.
19.10.2 TRANSMIT ONLY RESET
The Transmit Only Reset is performed by writing a ‘1’
to the TXRST bit (ECON1<7>). This resets the transmit
logic only. Other register and control blocks, such as
buffer management and host interface, are not affected
by a Transmit Only Reset event. To return to normal
operation, the TXRST bit must be cleared in software.
After clearing TXRST, firmware must not write to any
Ethernet module SFRs for at least 1.6 s. After the
delay, normal operation can resume.
19.10.3 RECEIVE ONLY RESET
The Receive Only Reset is performed by writing a ‘1’ to
the RXRST bit (ECON1<6>). This action resets receive
logic only. Other register and control blocks, such as the
buffer management and host interface blocks, are not
affected by a Receive Only Reset event. To return to
normal operation, the RXRST bit is cleared in software.
After clearing RXRST, firmware must not write to any
Ethernet module SFRs for at least 1.6 s. After the
delay, normal operation can resume.
 2011 Microchip Technology Inc.
DS39762F-page 267