PIC18F97J60_11 Datasheet, PDF (226/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
19.2.1.3 Transmit Buffer
Any space within the 8-Kbyte memory which is not
programmed as part of the receive FIFO buffer is consid-
ered to be the transmit buffer. The responsibility of
managing where packets are located in the transmit buf-
fer belongs to the application. Whenever the application
decides to transmit a packet, the ETXST and ETXND
Pointers are programmed with addresses specifying
where, within the transmit buffer, the particular packet to
transmit is located. The hardware does not check that the
start and end addresses do not overlap with the receive
buffer. To prevent buffer corruption, the firmware must not
transmit a packet while the ETXST and ETXND Pointers
are overlapping the receive buffer, or while the ETXND
Pointers are too close to the receive buffer. See
Section 19.5.2 “Transmitting Packets” for more
information.
19.2.1.4 Buffer Arbiter and Access Arbitration
The Ethernet buffer is clocked at one-half of the micro-
controller clock rate. Varying amounts of memory
access bandwidth are available depending on the clock
speed. The total bandwidth available, in bytes per sec-
ond, is equal to twice the instruction rate (2 * FCY or
FOSC/2). For example, at a system clock speed of
41.667 MHz, the total available memory bandwidth that
is available is 20.834 Mbyte/s. At an Ethernet signaling
rate of 10 Mbit/s, the Ethernet RX engine requires
1.25 Mbyte/s of buffer memory bandwidth to operate
without causing an overrun. If Full-Duplex mode is
used, an additional 1.25 Mbyte/s is required to allow for
simultaneous RX and TX activity.
Because of the finite available memory bandwidth, a
three-channel arbiter is used to allocate bandwidth
between the RX engine, the TX and DMA engines, and
the microcontroller’s CPU (i.e., the application access-
ing EDATA). The arbiter gives the EDATA register
accesses first priority, while all remaining bandwidth is
shared between the RX and TX/DMA blocks.
With arbitration, bandwidth limitations require that
some care be taken in balancing the needs of the mod-
ule’s hardware with that of the application. Accessing
the EDATA register too often may result in the RX or TX
blocks causing a buffer overrun or underrun, respec-
tively. If such a memory access failure occurs, the
BUFER bit (ESTAT<6>), and either the TXERIF or
RXERIF interrupt flag, becomes set, and a TX or RX
interrupt occurs (if enabled). In either case, the current
packet will be lost or aborted.
To eliminate the risk of lost packets, run the microcon-
troller core at higher speeds. Following the arbitration
restrictions, shown in Table 19-2, will prevent memory
access failures from occurring. Also, avoid using seg-
ments of application code which perform back-to-back
accesses of the EDATA register. Instead, insert one or
more instructions (including NOP instructions) between
each read or write to EDATA.
19.2.1.5 DMA Access to the Buffer
The integrated DMA controller must read from the
buffer when calculating a checksum, and it must read
and write to the buffer when copying memory. The DMA
follows the same wrapping rules as previously
described for the receive buffer. While it sequentially
reads, it will be subject to a wrapping condition at the
end of the receive buffer. All writes it does will not be
subject to any wrapping conditions. See Section 19.9
“Direct Memory Access Controller” for more
information.
TABLE 19-2: BUFFER ARBITRATION RESTRICTIONS VS. CLOCK SPEED
FOSC
(MHz)
FCY
(MHz)
Available Bandwidth (Mbyte/s)
Total After RX After TX
Application Restrictions
to Prevent Underrun/Overrun
41.667
31.250
25.000
20.833
13.889
12.500
8.333
6.250
4.167
2.778
10.42
7.81
6.25
5.21
3.47
3.13
2.08
1.56
1.04
0.69
20.83
15.63
12.50
10.42
6.94
6.25
4.17
3.13
2.08
1.39
19.58
14.38
11.25
9.17
5.69
5.00
2.92
1.88
0.83
0.14
18.33
13.13
10.00
7.92
4.44
3.75
1.67
0.63
<0
<0
Access EDATA no more than once every 2 TCY
Access EDATA no more than once every 2 TCY
Access EDATA no more than once every 2 TCY
Access EDATA no more than once every 2 TCY
Access EDATA no more than once every 2 TCY
Access EDATA no more than once every 2 TCY
Access EDATA no more than once every 3 TCY
Access EDATA no more than once every 5 TCY
Do not use DMA, do not use full duplex,
access EDATA no more than once every 3 TCY
Do not use DMA, do not use full duplex,
access EDATA no more than once every 10 TCY
DS39762F-page 226
 2011 Microchip Technology Inc.