PIC18F97J60_11 Datasheet, PDF (418/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
26.2.2 EXTENDED INSTRUCTION SET
ADDFSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Add Literal to FSR
ADDFSR f, k
0  k  63
f  [ 0, 1, 2 ]
FSR(f) + k  FSR(f)
None
1110 1000 ffkk kkkk
The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
1
1
Q2
Read
literal ‘k’
Q3
Process
Data
Q4
Write to
FSR
Example:
ADDFSR 2, 23h
Before Instruction
FSR2 = 03FFh
After Instruction
FSR2 = 0422h
ADDULNK
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
No
Operation
Add Literal to FSR2 and Return
ADDULNK k
0  k  63
FSR2 + k  FSR2,
(TOS) PC
None
1110 1000 11kk kkkk
The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURN is then
executed by loading the PC with the
TOS.
The instruction takes two cycles to
execute; a NOP is performed during
the second cycle.
This may be thought of as a special
case of the ADDFSR instruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
1
2
Q2
Read
literal ‘k’
No
Operation
Q3
Process
Data
No
Operation
Q4
Write to
FSR
No
Operation
Example:
ADDULNK 23h
Before Instruction
FSR2 =
PC
=
After Instruction
FSR2 =
PC
=
03FFh
0100h
0422h
(TOS)
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
DS39762F-page 418
 2011 Microchip Technology Inc.