PIC18F97J60_11 Datasheet, PDF (154/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
11.5 PORTD, TRISD and
LATD Registers
PORTD is implemented as a bidirectional port in two
ways:
• 64-pin and 80-pin devices: 3 bits (RD<2:0>)
• 100-pin devices: 8 bits (RD<7:0>)
The corresponding Data Direction register is TRISD.
Setting a TRISD bit (= 1) will make the corresponding
PORTD pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRISD
bit (= 0) will make the corresponding PORTD pin an
output (i.e., put the contents of the output latch on the
selected pin). All pins on PORTD are digital only and
tolerate voltages up to 5.5V.
The Output Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note: These pins are configured as digital inputs
on any device Reset.
On 100-pin devices, PORTD is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTD is the low-order byte of the multiplexed
address/data bus (AD<7:0>). The TRISD bits are also
overridden.
Each of the PORTD pins has a weak internal pull-up. A
single control bit can turn on all of the pull-ups. This is
performed by setting the RDPU bit (LATA<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on all device Resets.
On 100-pin devices, PORTD can also be configured to
function as an 8-bit wide, parallel microprocessor port
by setting the PSPMODE control bit (PSPCON<4>). In
this mode, parallel port data takes priority over other
digital I/O (but not the external memory interface).
When the parallel port is active, the input buffers are
TTL. For more information, refer to Section 11.11
“Parallel Slave Port (PSP)”.
EXAMPLE 11-4: INITIALIZING PORTD
CLRF
CLRF
MOVLW
MOVWF
PORTD
LATD
0CFh
TRISD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
DS39762F-page 154
 2011 Microchip Technology Inc.