PIC18F97J60_11 Datasheet, PDF (163/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 11-15: PORTG FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RG0/ECCP3/ RG0⁽¹⁾
0
P3A⁽¹⁾
1
O DIG LATG<0> data output.
I
ST PORTG<0> data input.
ECCP3⁽¹⁾ 0
O DIG ECCP3 compare and PWM output; takes priority over port data.
1
I
ST ECCP3 capture input.
P3A⁽¹⁾
0
O DIG ECCP3 Enhanced PWM output, Channel A; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RG1/TX2/
CK2⁽¹⁾
RG1⁽¹⁾
0
1
O DIG LATG<1> data output.
I
ST PORTG<1> data input.
TX2⁽¹⁾
1
O DIG Synchronous serial data output (EUSART2 module); takes priority over port data.
CK2⁽¹⁾
1
O DIG Synchronous serial data input (EUSART2 module). User must configure as an input.
1
I
ST Synchronous serial clock input (EUSART2 module).
RG2/RX2/
DT2⁽¹⁾
RG2⁽¹⁾
0
1
O DIG LATG<2> data output.
I
ST PORTG<2> data input.
RX2⁽¹⁾
1
I
ST Asynchronous serial receive data input (EUSART2 module).
DT2⁽¹⁾
1
O DIG Synchronous serial data output (EUSART2 module); takes priority over port data.
1
I
ST Synchronous serial data input (EUSART2 module). User must configure as an input.
RG3/CCP4/
RG3⁽¹⁾
0
P3D⁽¹⁾
1
O DIG LATG<3> data output.
I
ST PORTG<3> data input.
CCP4⁽¹⁾
0
O DIG CCP4 compare output and PWM output; takes priority over port data.
1
I
ST CCP4 capture input.
P3D⁽¹⁾
0
O DIG ECCP3 Enhanced PWM output, Channel D; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RG4/CCP5/
P1D
RG4
0
O DIG LATG<4> data output.
1
I
ST PORTG<4> data input.
CCP5
0
O DIG CCP5 compare output and PWM output; takes priority over port data.
1
I
ST CCP5 capture input.
P1D
0
O DIG ECCP1 Enhanced PWM output, Channel D; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RG5⁽²⁾
RG5⁽²⁾
0
O DIG LATG<0> data output.
1
I
ST PORTG<0> data input.
RG6⁽²⁾
RG6⁽²⁾
0
O DIG LATG<0> data output.
1
I
ST PORTG<0> data input.
RG7⁽²⁾
RG7⁽²⁾
0
O DIG LATG<0> data output.
1
I
ST PORTG<0> data input.
Legend:
Note 1:
2:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Implemented on 80-pin and 100-pin devices only.
Implemented on 100-pin devices only.
TABLE 11-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Name
PORTG
LATG
TRISG
Note 1:
2:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
Page:
RG7⁽¹⁾
RG6⁽¹⁾
RG5⁽¹⁾
RG4
RG3⁽²⁾
RG2⁽²⁾
RG1⁽²⁾
RG0⁽²⁾
72
LATG7⁽¹⁾ LATG6⁽¹⁾ LATG5⁽¹⁾ LATG4 LATG3⁽²⁾ LATG2⁽²⁾ LATG1⁽²⁾ LATG0⁽²⁾
72
TRISG7⁽¹⁾ TRISG6⁽¹⁾ TRISG5⁽¹⁾ TRISG4 TRISG3⁽²⁾ TRISG2⁽²⁾ TRISG1⁽²⁾ TRISG0⁽²⁾
71
Implemented on 100-pin devices only.
Implemented on 80-pin and 100-pin devices only.
 2011 Microchip Technology Inc.
DS39762F-page 163