PIC18F97J60_11 Datasheet, PDF (448/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
FIGURE 28-6:
PROGRAM MEMORY READ TIMING DIAGRAM
OSC1
A<19:16>
BA0
AD<15:0>
ALE
CE
Q1
Q2
Q3
Q4
Q1
Address
150
151
164
171
Address
160
155
167
166
168
169
Data from External
163
162
161
171A
OE
165
Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C, unless otherwise stated.
Q2
Address
Address
TABLE 28-10: CLKO AND I/O TIMING REQUIREMENTS
Param.
No
Symbol
Characteristics
Min
Typ
Max
Units
150
151
155
160
161
162
163
164
165
166
167
168
169
171
171A
TadV2alL Address Out Valid to ALE 
(address setup time)
TalL2adl ALE  to Address Out Invalid
(address hold time)
TalL2oeL ALE to OE 
TadZ2oeL AD high-Z to OE (bus release to OE)
ToeH2adD OE  to AD Driven
TadV2oeH Least Significant Data Valid before OE 
(data setup time)
ToeH2adl OE  to Data In Invalid (data hold time)
TalH2alL ALE Pulse Width
ToeL2oeH OE Pulse Width
TalH2alH ALE  to ALE  (cycle time)
Tacc
Address Valid to Data Valid
Toe
OE  to Data Valid
TalL2oeH ALE to OE 
TalH2csL Chip Enable Active to ALE 
TubL2oeH AD Valid to Chip Enable Active
0.25 TCY – 10
—
5
—
—
ns
—
ns
10
0.125 TCY
—
ns
0
—
—
ns
0.125 TCY – 5
—
—
ns
20
—
—
ns
0
—
—
ns
—
TCY
—
ns
0.5 TCY – 5 0.5 TCY
—
ns
—
0.25 TCY
—
ns
0.75 TCY – 25
—
—
ns
—
0.5 TCY – 25 ns
0.625 TCY – 10
—
0.625 TCY + 10 ns
0.25 TCY – 20
—
—
ns
—
—
10
ns
DS39762F-page 448
 2011 Microchip Technology Inc.