PIC18F97J60_11 Datasheet, PDF (399/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
LFSR
Load FSR
Syntax:
LFSR f, k
Operands:
Operation:
Status Affected:
0f2
0  k  4095
k  FSRf
None
Encoding:
Description:
1110
1111
1110 00ff k₁₁kkk
0000 k₇kkk kkkk
The 12-bit literal ‘k’ is loaded into the
File Select Register pointed to by ‘f’.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Decode
Q2
Read literal
‘k’ MSB
Decode
Read literal
‘k’ LSB
Q3
Process
Data
Process
Data
Q4
Write
literal ‘k’
MSB to
FSRfH
Write literal
‘k’ to FSRfL
Example:
LFSR 2, 3ABh
After Instruction
FSR2H
FSR2L
= 03h
= ABh
MOVF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Move f
MOVF f {,d {,a}}
0  f  255
d  [0,1]
a  [0,1]
f  dest
N, Z
0101 00da ffff ffff
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write
W
Example:
MOVF
Before Instruction
REG
=
W
=
After Instruction
REG
=
W
=
REG, 0, 0
22h
FFh
22h
22h
 2011 Microchip Technology Inc.
DS39762F-page 399