PIC18F97J60_11 Datasheet, PDF (486/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
Serial Clock .............................................................. 269
Serial Data In ........................................................... 269
Serial Data Out ........................................................ 269
Slave Mode .............................................................. 275
Slave Select ............................................................. 269
Slave Select Synchronization .................................. 275
SPI Clock ................................................................. 274
Typical Connection .................................................. 273
SSPOV ............................................................................. 304
SSPOV Status Flag .......................................................... 304
SSPSTAT Register
R/W Bit ..................................................................... 286
SSPxSTAT Register
R/W Bit ..................................................................... 284
......................................................................................... 269
SUBFSR ........................................................................... 421
SUBFWB .......................................................................... 410
SUBLW ............................................................................ 411
SUBULNK ........................................................................ 421
SUBWF ............................................................................ 411
SUBWFB .......................................................................... 412
SWAPF ............................................................................ 412
T
Table Pointer Operations (table) ...................................... 108
Table Reads/Table Writes .................................................. 83
TBLRD ............................................................................. 413
TBLWT ............................................................................. 414
Timer0 .............................................................................. 171
Associated Registers ............................................... 173
Clock Source Select (T0CS Bit) ............................... 172
Operation ................................................................. 172
Overflow Interrupt .................................................... 173
Prescaler .................................................................. 173
Prescaler Assignment (PSA Bit) .............................. 173
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 173
Prescaler, Switching Assignment ............................. 173
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 172
Source Edge Select (T0SE Bit) ................................ 172
Timer1 .............................................................................. 175
16-Bit Read/Write Mode ........................................... 177
Associated Registers ............................................... 179
Considerations in Asynchronous Counter Mode ...... 178
Interrupt .................................................................... 178
Operation ................................................................. 176
Oscillator .......................................................... 175, 177
Layout Considerations ..................................... 177
Overflow Interrupt .................................................... 175
Resetting, Using the ECCPx Special
Event Trigger ................................................... 178
Special Event Trigger (ECCP) ................................. 202
TMR1H Register ...................................................... 175
TMR1L Register ....................................................... 175
Use as a Clock Source ............................................ 177
Use as a Real-Time Clock ....................................... 178
Timer2 .............................................................................. 180
Associated Registers ............................................... 181
Interrupt .................................................................... 181
Operation ................................................................. 180
Output ...................................................................... 181
PR2 Register .................................................... 194, 203
TMR2 to PR2 Match Interrupt .................................. 203
Timer3 .............................................................................. 183
16-Bit Read/Write Mode .......................................... 185
Associated Registers ............................................... 185
Operation ................................................................. 184
Oscillator .......................................................... 183, 185
Overflow Interrupt ............................................ 183, 185
Resetting Using the ECCPx Special
Event Trigger ................................................... 185
TMR3H Register ...................................................... 183
TMR3L Register ....................................................... 183
Timer4 .............................................................................. 187
Associated Registers ............................................... 188
Operation ................................................................. 187
Output, PWM Time Base ......................................... 188
Postscaler. See Postscaler, Timer4.
PR4 Register ................................................... 187, 194
Prescaler. See Prescaler, Timer4.
TMR4 Register ......................................................... 187
TMR4 to PR4 Match Interrupt .......................... 187, 188
Timing Diagrams
A/D Conversion ........................................................ 462
Asynchronous Reception, RXDTP = 0
(RXx Not Inverted) ........................................... 329
Asynchronous Transmission (Back-to-Back),
TXCKP = 0 (TXx Not Inverted) ........................ 326
Asynchronous Transmission, TXCKP = 0
(TXx Not Inverted) ........................................... 326
Automatic Baud Rate Calculation ............................ 324
Auto-Wake-up Bit (WUE) During Normal
Operation ......................................................... 331
Auto-Wake-up Bit (WUE) During Sleep ................... 331
Baud Rate Generator with Clock Arbitration ............ 301
BRG Overflow Sequence ......................................... 324
BRG Reset Due to SDAx Arbitration During
Start Condition ................................................. 310
Capture/Compare/PWM (Including
ECCPx Modules) ............................................. 452
CLKO and I/O .......................................................... 447
Clock Synchronization ............................................. 294
Clock/Instruction Cycle .............................................. 84
EUSARTx Synchronous Receive
(Master/Slave) ................................................. 461
EUSARTx Synchronous Transmission
(Master/Slave) ................................................. 461
Example SPI Master Mode (CKE = 0) ..................... 453
Example SPI Master Mode (CKE = 1) ..................... 454
Example SPI Slave Mode (CKE = 0) ....................... 455
Example SPI Slave Mode (CKE = 1) ....................... 456
External Clock (All Modes Except PLL) ................... 445
External Memory Bus for Sleep (Extended
Microcontroller Mode) .............................. 122, 124
External Memory Bus for TBLRD (Extended
Microcontroller Mode) .............................. 122, 124
Fail-Safe Clock Monitor ........................................... 372
First Start Bit ............................................................ 302
Full-Bridge PWM Output .......................................... 208
Half-Bridge PWM Output ......................................... 207
I²C Acknowledge Sequence .................................... 307
I²C Bus Collision During a Repeated
Start Condition (Case 1) .................................. 311
I²C Bus Collision During a Repeated
Start Condition (Case 2) .................................. 311
I²C Bus Collision During a Stop Condition (Case 1) 312
DS39762F-page 486
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