PIC18F97J60_11 Datasheet, PDF (93/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 6-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values on Details on
POR, BOR Page:
T3CON
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 71, 183
PSPCON⁽⁵⁾
IBF
OBF
IBOV
PSPMODE
—
—
—
—
0000 ---- 71, 169
SPBRG1
EUSART1 Baud Rate Generator Register Low Byte
0000 0000 71, 320
RCREG1 EUSART1 Receive Register
0000 0000 71, 327
TXREG1
EUSART1 Transmit Register
xxxx xxxx 71, 329
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 71, 320
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 71, 320
EECON2
Program Memory Control Register (not a physical register)
---- ---- 71, 106
EECON1
—
—
—
FREE
WRERR
WREN
WR
—
---0 x00- 71, 107
IPR3
SSP2IP⁽⁵⁾ BCL2IP⁽⁵⁾ RC2IP⁽⁶⁾
TX2IP⁽⁶⁾
TMR4IP
CCP5IP
CCP4IP
CCP3IP 1111 1111 71, 142
PIR3
SSP2IF⁽⁵⁾ BCL2IF⁽⁵⁾ RC2IF⁽⁶⁾
TX2IF⁽⁶⁾
TMR4IF
CCP5IF
CCP4IF
CCP3IF 0000 0000 71, 136
PIE3
SSP2IE⁽⁵⁾ BCL2IE⁽⁵⁾ RC2IE⁽⁶⁾
TX2IE⁽⁶⁾
TMR4IE
CCP5IE
CCP4IE
CCP3IE 0000 0000 71, 139
IPR2
OSCFIP
CMIP
ETHIP
r
BCL1IP
—
TMR3IP
CCP2IP 1111 1-11 71, 141
PIR2
OSCFIF
CMIF
ETHIF
r
BCL1IF
—
TMR3IF
CCP2IF 0000 0-00 71, 135
PIE2
OSCFIE
CMIE
ETHIE
r
BCL1IE
—
TMR3IE
CCP2IE 0000 0-00 71, 138
IPR1
PSPIP⁽⁹⁾
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP 1111 1111 71, 140
PIR1
PSPIF⁽⁹⁾
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF 0000 0000 71, 134
PIE1
PSPIE⁽⁹⁾
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE 0000 0000 71, 137
MEMCON^(5,7) EBDIS
—
WAIT1
WAIT0
—
—
WM1
WM0 0-00 --00 71, 116
OSCTUNE
PPST1
PLLEN⁽⁸⁾
PPST0
PPRE
—
—
—
—
0000 ---- 71, 51
TRISJ⁽⁶⁾
TRISJ7⁽⁵⁾ TRISJ6⁽⁵⁾ TRISJ5⁽⁶⁾ TRISJ4⁽⁶⁾ TRISJ3⁽⁵⁾ TRISJ2⁽⁵⁾ TRISJ1⁽⁵⁾ TRISJ0⁽⁵⁾ 1111 1111 71, 167
TRISH⁽⁶⁾
TRISH7⁽⁶⁾ TRISH6⁽⁶⁾ TRISH5⁽⁶⁾ TRISH4⁽⁶⁾ TRISH3⁽⁶⁾ TRISH2⁽⁶⁾ TRISH1⁽⁶⁾ TRISH0⁽⁶⁾ 1111 1111 71, 165
TRISG
TRISG7⁽⁵⁾ TRISG6⁽⁵⁾ TRISG5⁽⁵⁾ TRISG4 TRISG3⁽⁶⁾ TRISG2⁽⁶⁾ TRISG1⁽⁶⁾ TRISG0⁽⁶⁾ 1111 1111 71, 163
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1 TRISF0⁽⁵⁾ 1111 1111 71, 161
TRISE
TRISE7⁽⁶⁾ TRISE6⁽⁶⁾ TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0 1111 1111 71, 159
TRISD
TRISD7⁽⁵⁾ TRISD6⁽⁵⁾ TRISD5⁽⁵⁾ TRISD4⁽⁵⁾ TRISD3⁽⁵⁾ TRISD2
TRISD1
TRISD0 1111 1111 71, 156
TRISC
TRISC7 TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0 1111 1111 71, 153
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0 1111 1111 71, 150
TRISA
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0 --11 1111 71, 147
LATJ⁽⁶⁾
LATJ7⁽⁵⁾
LATJ6⁽⁵⁾
LATJ5⁽⁶⁾
LATJ4⁽⁶⁾
LATJ3⁽⁵⁾
LATJ2⁽⁵⁾
LATJ1⁽⁵⁾
LATJ0⁽⁵⁾ xxxx xxxx 71, 167
LATH⁽⁶⁾
LATH7⁽⁶⁾ LATH6⁽⁶⁾
LATH5⁽⁶⁾
LATH4⁽⁶⁾
LATH3⁽⁶⁾
LATH2⁽⁶⁾
LATH1⁽⁶⁾
LATH0⁽⁶⁾ xxxx xxxx 71, 165
LATG
LATG7⁽⁵⁾ LATG6⁽⁵⁾
LATG5⁽⁵⁾
LATG4
LATG3⁽⁶⁾ LATG2⁽⁶⁾ LATG1⁽⁶⁾ LATG0⁽⁶⁾ xxxx xxxx 72, 163
LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0⁽⁵⁾ xxxx xxxx 72, 161
LATE
LATE7⁽⁶⁾ LATE6⁽⁶⁾
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0 xxxx xxxx 72, 159
LATD
LATD7⁽⁵⁾ LATD6⁽⁵⁾
LATD5⁽⁵⁾
LATD4⁽⁵⁾
LATD3⁽⁵⁾
LATD2
LATD1
LATD0 xxxx xxxx 72, 156
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0 xxxx xxxx 72, 153
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0 xxxx xxxx 72, 150
LATA
RDPU
REPU
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0 00xx xxxx 72, 147
PORTJ⁽⁶⁾
RJ7⁽⁵⁾
RJ6⁽⁵⁾
RJ5⁽⁶⁾
RJ4⁽⁶⁾
RJ3⁽⁵⁾
RJ2⁽⁵⁾
RJ1⁽⁵⁾
RJ0⁽⁵⁾ xxxx xxxx 72, 167
PORTH⁽⁶⁾
RH7⁽⁶⁾
RH6⁽⁶⁾
RH5⁽⁶⁾
RH4⁽⁶⁾
RH3⁽⁶⁾
RH2⁽⁶⁾
RH1⁽⁶⁾
RH0⁽⁶⁾ 0000 xxxx 72, 165
PORTG
RG7⁽⁵⁾
RG6⁽⁵⁾
RG5⁽⁵⁾
RG4
RG3⁽⁶⁾
RG2⁽⁶⁾
RG1⁽⁶⁾
RG0⁽⁶⁾ 111x xxxx 72, 163
Legend: x = unknown; u = unchanged; - = unimplemented, read as ‘0’; q = value depends on condition; r = reserved bit, do not modify. Shaded cells
are unimplemented, read as ‘0’.
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
2: Bit 21 of the PC is only available in Serial Programming modes.
3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
4: Alternate names and definitions for these bits when the MSSP module is operating in I²C™ Slave mode.
5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown
apply only to 100-pin devices.
6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as ‘0’. Reset
values are shown for 100-pin devices.
7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’.
8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’.
9: Implemented in 100-pin devices in Microcontroller mode only.
 2011 Microchip Technology Inc.
DS39762F-page 93