PIC18F97J60_11 Datasheet, PDF (286/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
20.4.3.3 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPxSTAT
register is cleared. The received address is loaded into
the SSPxBUF register and the SDAx line is held low
(ACK).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit, BF (SSPxSTAT<0>),
is set, or bit, SSPOV (SSPxCON1<6>), is set.
An MSSP interrupt is generated for each data transfer
byte. The interrupt flag bit, SSPxIF, must be cleared in
software. The SSPxSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPxCON2<0> = 1), SCKx/SCLx
(RC3 or RD6) will be held low (clock stretch) following
each data transfer. The clock must be released by
setting bit, CKP (SSPxCON1<4>). See Section 20.4.4
“Clock Stretching” for more details.
20.4.3.4 Transmission
When the R/W bit of the incoming address byte is set and
an address match occurs, the R/W bit of the SSPxSTAT
register is set. The received address is loaded into the
SSPxBUF register. The ACK pulse will be sent on the
ninth bit and pin RC3 or RD6 is held low, regardless of
SEN (see Section 20.4.4 “Clock Stretching” for more
details). By stretching the clock, the master will be unable
to assert another clock pulse until the slave is done
preparing the transmit data. The transmit data must be
loaded into the SSPxBUF register which also loads the
SSPxSR register. Then, pin, RC3 or RD6, should be
enabled by setting bit, CKP (SSPxCON1<4>). The eight
data bits are shifted out on the falling edge of the SCLx
input. This ensures that the SDAx signal is valid during
the SCLx high time (Figure 20-10).
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCLx input pulse. If the SDAx
line is high (not ACK), then the data transfer is complete.
In this case, when the ACK is latched by the slave, the
slave logic is reset (resets SSPxSTAT register) and the
slave monitors for another occurrence of the Start bit. If
the SDAx line was low (ACK), the next transmit data
must be loaded into the SSPxBUF register. Again, pin,
RC3 or RD6, must be enabled by setting bit, CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPxIF bit must be cleared in software and
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of
the ninth clock pulse.
DS39762F-page 286
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