PIC18F97J60_11 Datasheet, PDF (487/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
I²C Bus Collision During a Stop
Condition (Case 2) ........................................... 312
I²C Bus Collision During Start
Condition (SCLx = 0) ....................................... 310
I²C Bus Collision During Start
Condition (SDAx Only) ..................................... 309
I²C Bus Collision for Transmit and Acknowledge .... 308
I²C Bus Data ............................................................ 457
I²C Bus Start/Stop Bits ............................................. 457
I²C Master Mode (7 or 10-Bit Transmission) ........... 305
I²C Master Mode (7-Bit Reception) .......................... 306
I²C Slave Mode (10-Bit Reception, SEN = 0,
ADMSK = 01001) ............................................. 291
I²C Slave Mode (10-Bit Reception, SEN = 0) .......... 290
I²C Slave Mode (10-Bit Reception, SEN = 1) .......... 296
I²C Slave Mode (10-Bit Transmission) ..................... 292
I²C Slave Mode (7-Bit Reception, SEN = 0,
ADMSK = 01011) ............................................. 288
I²C Slave Mode (7-Bit Reception, SEN = 0) ............ 287
I²C Slave Mode (7-Bit Reception, SEN = 1) ............ 295
I²C Slave Mode (7-Bit Transmission) ....................... 289
I²C Slave Mode General Call Address
Sequence (7 or 10-Bit Addressing Mode) ........ 297
I²C Stop Condition Receive or Transmit Mode ........ 307
Master SSP I²C Bus Data ........................................ 459
Master SSP I²C Bus Start/Stop Bits ........................ 459
Parallel Slave Port (PSP) Read ............................... 170
Parallel Slave Port (PSP) Write ............................... 169
Program Memory Read ............................................ 448
Program Memory Write ............................................ 449
PWM Auto-Shutdown (P1RSEN = 0,
Auto-Restart Disabled) .................................... 213
PWM Auto-Shutdown (P1RSEN = 1,
Auto-Restart Enabled) ..................................... 213
PWM Direction Change ........................................... 210
PWM Direction Change at Near
100% Duty Cycle ............................................. 210
PWM Output ............................................................ 194
Repeated Start Condition ......................................... 303
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ..... 450
Send Break Character Sequence ............................ 332
Slave Synchronization ............................................. 275
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 67
SPI Mode (Master Mode) ......................................... 274
SPI Mode (Slave Mode, CKE = 0) ........................... 276
SPI Mode (Slave Mode, CKE = 1) ........................... 276
Synchronous Reception (Master Mode, SREN) ...... 335
Synchronous Transmission ...................................... 333
Synchronous Transmission (Through TXEN) .......... 334
Time-out Sequence on Power-up (MCLR
Not Tied to VDD), Case 1 ................................... 66
Time-out Sequence on Power-up (MCLR
Not Tied to VDD), Case 2 ................................... 67
Time-out Sequence on Power-up (MCLR Tied
to VDD, VDD Rise < TPWRT) ................................ 66
Timer0 and Timer1 External Clock .......................... 451
Transition for Entry to Idle Mode ................................ 60
Transition for Entry to SEC_RUN Mode .................... 57
Transition for Entry to Sleep Mode ............................ 59
Transition for Two-Speed Start-up
(INTRC to HSPLL) ........................................... 370
Transition for Wake From Idle to Run Mode .............. 60
Transition for Wake From Sleep Mode (HSPLL) ....... 59
Transition From RC_RUN Mode to
PRI_RUN Mode ................................................. 58
Transition From SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 57
Transition to RC_RUN Mode ..................................... 58
Timing Diagrams and Specifications
AC Characteristics
Internal RC Accuracy ....................................... 446
Capture/Compare/PWM Requirements
(Including ECCPx Modules) ............................ 452
CLKO and I/O Requirements ........................... 447, 448
EUSARTx Synchronous Receive Requirements ..... 461
EUSARTx Synchronous Transmission
Requirements .................................................. 461
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 453
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 454
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 455
Example SPI Slave Mode Requirements (CKE = 1) 456
External Clock Requirements .................................. 445
I²C Bus Data Requirements (Slave Mode) .............. 458
I²C Bus Start/Stop Bits Requirements
(Slave Mode) ................................................... 457
Master SSP I²C Bus Data Requirements ................ 460
Master SSP I²C Bus Start/Stop Bits
Requirements .................................................. 459
Parallel Slave Port Requirements ............................ 452
PLL Clock ................................................................ 446
Program Memory Write Requirements .................... 449
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 450
Timer0 and Timer1 External Clock
Requirements .................................................. 451
Top-of-Stack Access .......................................................... 81
TRISE Register
PSPMODE Bit ......................................................... 168
TSTFSZ ........................................................................... 415
Two-Speed Start-up ................................................. 359, 370
Two-Word Instructions
Example Cases ......................................................... 85
TXSTAx Register
BRGH Bit ................................................................. 319
V
VDDCORE/VCAP Pin .......................................... 369, 442, 369
W
Watchdog Timer (WDT) ........................................... 359, 367
Associated Registers ............................................... 368
Control Register ....................................................... 367
Programming Considerations .................................. 367
WCOL ...................................................... 302, 303, 304, 307
WCOL Status Flag ................................... 302, 303, 304, 307
WWW Address ................................................................ 488
WWW, On-Line Support ...................................................... 9
X
XORLW ........................................................................... 415
XORWF ........................................................................... 416
 2011 Microchip Technology Inc.
DS39762F-page 487