PIC18F97J60_11 Datasheet, PDF (336/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 21-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF
RBIF
69
PIR1
PSPIF
ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
71
PIE1
PSPIE
ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
71
IPR1
PSPIP
ADIP
RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
71
PIR3
SSP2IF BCL2IF RC2IF⁽¹⁾ TX2IF TMR4IF CCP5IF CCP4IF CCP3IF
71
PIE3
SSP2IE BCL2IE RC2IE⁽¹⁾ TX2IE TMR4IE CCP5IE CCP4IE CCP3IE
71
IPR3
SSP2IP BCL2IP RC2IP⁽¹⁾ TX2IP TMR4IP CCP5IP CCP4IP CCP3IP
71
RCSTAx
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
71
RCREGx EUSARTx Receive Register
71
TXSTAx
CSRC
TX9
TXEN
SYNC SENDB BRGH
TRMT
TX9D
71
BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16
—
WUE ABDEN
72
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
72
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
72
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as ‘0’.
DS39762F-page 336
 2011 Microchip Technology Inc.