PIC18F97J60_11 Datasheet, PDF (53/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
3.7.1 OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 3-2) controls several
aspects of the device clock’s operation, both in
full-power operation and in power-managed modes.
The System Clock Select bits, SCS<1:0>, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC<2:0> Configura-
tion bits), the secondary clock (Timer1 oscillator) and
the internal oscillator. The clock source changes after
one or more of the bits are changed, following a brief
clock transition interval.
The OSTS (OSCCON<3>) and T1RUN (T1CON<6>)
bits indicate which clock source is currently providing
the device clock. The T1RUN bit indicates when the
Timer1 oscillator is providing the device clock in
secondary clock modes. In power-managed modes,
only one of these bits will be set at any time. If neither
bit is set, the INTRC source is providing the clock, or
the internal oscillator has just started and is not yet
stable.
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 4.0
“Power-Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control reg-
ister (T1CON<3>). If the Timer1 oscillator
is not enabled, then any attempt to select
a secondary clock source will be ignored.
2: It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEP instruction or a very
long delay may occur while the Timer1
oscillator starts.
REGISTER 3-2:
R/W-0
IDLEN
bit 7
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
U-0
U-0
R-q
U-0
—
—
—
OSTS⁽¹⁾
—
R/W-0
SCS1
R/W-0
SCS0
bit 0
Legend:
R = Readable bit
-n = Value at POR
q = Value determined by configuration
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6-4
bit 3
bit 2
bit 1-0
IDLEN: Idle Enable bit
1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction
Unimplemented: Read as ‘0’
OSTS: Oscillator Status bit⁽¹⁾
1 = Device is running from oscillator source defined when SCS<1:0> = 00
0 = Device is running from oscillator source defined when SCS<1:0> = 01, 10 or 11
Unimplemented: Read as ‘0’
SCS<1:0>: System Clock Select bits
11 = Internal oscillator
10 = Primary oscillator
01 = Timer1 oscillator
When FOSC2 = 1;
00 = Primary oscillator
When FOSC2 = 0;
00 = Internal oscillator
Note 1: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
 2011 Microchip Technology Inc.
DS39762F-page 53