PIC18F97J60_11 Datasheet, PDF (223/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
19.2.1
ETHERNET BUFFER AND BUFFER
POINTER REGISTERS
The Ethernet buffer contains the transmit and receive
memory used by the Ethernet controller. The entire
buffer is 8 Kbytes, divided into separate receive and
transmit buffer spaces. The sizes and locations of
transmit and receive memory are fully definable using
the pointers in the Ethernet SFR space. The organiza-
tion of the memory space and the relationships of the
pointers are shown in Figure 19-5.
The buffer is always accessible through the EDATA and
Ethernet Pointer SFRs, regardless of whether or not the
Ethernet module is enabled. This makes the buffer
potentially useful for applications requiring large amounts
of RAM and that do not require Ethernet communication.
In these instances, disabling the Ethernet module
reduces overall power usage but does not prevent buffer
access.
19.2.1.1 Reading and Writing to the Buffer
The Ethernet buffer contents are accessed through the
EDATA register, which acts as a window from the
microcontroller data bus into the buffer. The location of
that window is determined by either the ERDPT or
EWRPT Pointers, depending on the operation being
performed. For example, writing to EDATA causes a
write to the Ethernet buffer at the address currently
indicated by the EWRPT register pair. Similarly, moving
the contents of EDATA to another register actually
moves the buffer contents at the address indicated by
the ERDPT Pointer.
When the AUTOINC bit (ECON2<7>) is set, the asso-
ciated Read or Write Pointer increments by one
address following each read or write operation. This
eliminates the need to constantly update a pointer after
each read or write, simplifying multiple sequential
operations. By default, the AUTOINC bit is set.
While sequentially reading from the receive buffer, a
wrapping condition will occur at the end of the receive
buffer. A read of EDATA, from the address programmed
into the ERXND Pointers, will cause the ERDPT
registers to be incremented to the value contained in
the ERXST Pointers. Writing to the buffer, on the other
hand, does not result in automatic wrapping.
By design, the Ethernet memory buffer is unable to
support a set of operations where EDATA is used as
both an operand and a data destination. Failure to
observe these restrictions will result in a corrupted read
or write. Also, due to the read-modify-write architecture
of the processor core, single-cycle instructions, which
write to the EDATA register, will have a side effect of
automatically incrementing the ERDPT registers when
AUTOINC is set. Using double-cycle MOVFF, MOVSF
and MOVSS instructions to write to EDATA will not affect
the Read Pointer. See the following note for examples.
Note:
Any single instruction that performs both a
read and write to the EDATA SFR register
will result in a corrupted operation.
Unsupported examples:
INCF EDATA, F
XORWF EDATA, F
MOVFF EDATA, EDATA
MOVFF INDF0, EDATA; (FSR0 = F61h)
Instructions that only perform one read or
one write are permitted.
Supported examples:
INCF EDATA, W
MOVF EDATA, W
MOVFF INDF0, EDATA; (FSR0 != F61h)
Single-cycle, write-only instructions, while
valid, will have a side effect of also incre-
menting the ERDPT registers when
AUTOINC is enabled.
Examples incrementing both ERDPT and
EWRPT:
CLRF EDATA
SETF EDATA
MOVWF EDATA
 2011 Microchip Technology Inc.
DS39762F-page 223