PIC18F97J60_11 Datasheet, PDF (243/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
19.3.1.1 Receive Error Interrupt (RXERIF)
The receive error interrupt is used to indicate that a
packet being received was aborted due to an error
condition. Three errors are possible:
1. No buffer space is available to store the
incoming packet (buffer overflow);
2. Receiving another packet would cause the
EPKTCNT counter to overflow, because it
already contains the value, 255; or
3. The Ethernet RX hardware was not allocated
enough memory bandwidth to write the
incoming data to the buffer.
When a packet is being received and the receive error
occurs, the packet being received will be aborted (per-
manently lost) and the RXERIF bit will be set to ‘1’.
Once set, RXERIF can only be cleared by firmware or
by a Reset condition. If the receive error interrupt and
Ethernet interrupt are enabled (both RXERIE and
ETHIE are set), an Ethernet interrupt is generated. If
the receive error interrupt is not enabled (either
RXERIE or ETHIE is cleared), the application may poll
RXERIF and take appropriate action.
Normally, upon the first two receive error conditions
(buffer overflow or potential EPKTCNT overflow), the
application would process any packets pending from
the receive buffer, and then make additional room for
future packets by advancing the ERXRDPT registers
(low byte first) and decrementing the EPKTCNT regis-
ter. See Section 19.5.3.3 “Freeing Receive Buffer
Space” for more information on processing packets.
Once processed, the application should clear the
RXERIF bit.
The third condition (insufficient RX memory bandwidth)
can be identified by checking if the BUFER bit
(ESTAT<6>) has been set. Memory access errors that
set BUFER are generally transient in nature, and do not
require run-time resolution. Adjustments to the applica-
tion and its allocation of buffer memory bandwidth may
be necessary if BUFER errors are frequent or
persistent.
19.3.1.2 Transmit Error Interrupt (TXERIF)
The transmit error interrupt is used to indicate that a
transmit abort has occurred. An abort can occur
because of any of the following conditions:
1. More than 15 collisions occurred while attempting
to transmit a given packet.
2. A late collision (collision after 64 bytes of a
packet had been transmitted) has occurred.
3. The transmission was unable to gain an oppor-
tunity to transmit the packet because the
medium was constantly occupied for too long.
The deferral limit was reached and the DEFER
bit (MACON4<6>) was clear.
4. An attempt to transmit a packet larger than the
maximum frame length, defined by the
MAMXFL registers, was made without setting
the HFRMEN bit (MACON3<2>) or per-packet
POVERRIDE and PHUGEEN bits.
5. The Ethernet buffer did not have enough mem-
ory bandwidth to maintain the required 10 Mbit/s
transfer rate (buffer underrun).
Upon any of these conditions, the TXERIF flag is set to
‘1’. Once set, it can only be cleared by firmware or by a
Reset condition. If the transmit error interrupt is
enabled (TXERIE and ETHIE are both set), an Ethernet
interrupt is generated. If the transmit error interrupt is
not enabled (either TXERIE or ETHIE is cleared), the
application may poll TXERIF and take appropriate
action. Once the interrupt is processed, the flag bit
should be cleared.
After a transmit abort, the TXRTS bit (ECON1<3>) will
be cleared, the TXABRT bit (ESTAT<1>) becomes set
and the transmit status vector will be written at the
ETXND registers + 1. The MAC will not automatically
attempt to retransmit the packet. The application may
wish to read the transmit status vector and BUFER bit
to determine the cause of the abort. After determining
the problem and solution, the application should clear
the BUFER (if set) and TXABRT bits so that future
aborts can be detected accurately.
In Full-Duplex mode, Conditions 4 and 5 are the only
ones that should cause this interrupt. Condition 5 can
be further distinguished as it also sets the BUFER bit.
Collisions and other problems related to sharing the
network are not possible on full-duplex networks. The
conditions, which cause the transmit error interrupt,
meet the requirements of the transmit interrupt. As a
result, when this interrupt occurs, TXIF will also be
simultaneously set.
19.3.1.3 Transmit Interrupt (TXIF)
The transmit interrupt is used to indicate that the
requested packet transmission has ended (the TXRTS
bit has transitioned from ‘1’ to ‘0’). Upon transmission
completion, abort, or transmission cancellation by the
application, the TXIF flag will be set to ‘1’. If the
application did not clear the TXRTS bit, and the
TXABRT bit is not set, the packet was successfully
transmitted. Once TXIF is set, it can only be cleared in
software or by a Reset condition. If the transmit
interrupt is enabled (TXIE and ETHIE are both set), an
interrupt is generated. If the transmit interrupt is not
enabled (either TXIE or ETHIE is cleared), the
application may poll the TXIF bit and take appropriate
action.
 2011 Microchip Technology Inc.
DS39762F-page 243