PIC18F97J60_11 Datasheet, PDF (269/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
20.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
20.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D Converters, etc. The MSSP mod-
ule can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I²C™)
- Full Master mode
- Slave mode (with general address call)
The I²C interface supports the following modes in
hardware:
• Master mode
• Multi-Master mode
• Slave mode
The 64-pin and 80-pin devices of the PIC18F97J60
family have one MSSP module, designated as MSSP1.
The 100-pin devices have two MSSP modules, desig-
nated as MSSP1 and MSSP2. Each module operates
independently of the other.
Note:
Throughout this section, generic refer-
ences to an MSSP module in any of its
operating modes may be interpreted as
being equally applicable to MSSP1 or
MSSP2. Register names and module I/O
signals use the generic designator, ‘x’, to
indicate the use of a numeral to distin-
guish a particular module when required.
Control bit names are not individuated.
20.2 Control Registers
Each MSSP module has three associated control
registers. These include a status register (SSPxSTAT)
and two control registers (SSPxCON1 and SSPxCON2).
The use of these registers and their individual configura-
tion bits differ significantly depending on whether the
MSSP module is operating in SPI or I²C mode.
Additional details are provided under the individual
sections.
Note:
In devices with more than one MSSP
module, it is very important to pay close
attention to the SSPxCON register
names. SSP1CON1 and SSP1CON2
control different operational aspects of the
same module, while SSP1CON1 and
SSP2CON1 control the same features for
two different modules.
20.3 SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
• Serial Data Out (SDOx) – RC5/SDO1 (or
RD4/SDO2 for 100-pin devices)
• Serial Data In (SDIx) – RC4/SDI1/SDA1 (or
RD5/SDI2/SDA2 for 100-pin devices)
• Serial Clock (SCKx) – RC3/SCK1/SCL1 (or
RD6/SCK2/SCL2 for 100-pin devices)
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SSx) – RF7/SS1 (or RD7/SS2 for
100-pin devices)
Figure 20-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 20-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
Read
Internal
Data Bus
Write
SSPxBUF reg
SDIx
SDOx
SSPxSR reg
bit 0
Shift
Clock
SSx
SCKx
SSx Control
Enable
Edge
Select
2
Clock Select
SSPM<3:0>
SMP:CKE ₄
2
( ) TMR2 Output
2
Edge
Select
Prescaler ^TOSC
4, 16, 64
Data to TXx/RXx in SSPxSR
TRIS bit
 2011 Microchip Technology Inc.
DS39762F-page 269