PIC18F97J60_11 Datasheet, PDF (159/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 11-11: PORTE FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RE5/AD13/
RE5
0
P1C
1
AD13⁽¹⁾
x
x
P1C⁽³⁾
0
O
DIG LATE<5> data output.
I
ST PORTE<5> data input; weak pull-up when REPU bit is set.
O
DIG External memory interface, Address/Data Bit 13 output.⁽²⁾
I
TTL External memory interface, Data Bit 13 input.⁽²⁾
O
DIG ECCP1 Enhanced PWM output, Channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE6/AD14/
RE6
0
P1B⁽⁴⁾
1
AD14⁽¹⁾
x
x
P1B⁽³⁾
0
O
DIG LATE<6> data output.
I
ST PORTE<6> data input; weak pull-up when REPU bit is set.
O
DIG External memory interface, Address/Data Bit 14 output.⁽²⁾
I
TTL External memory interface, Data Bit 14 input.⁽²⁾
O
DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE7/AD15/
RE7
0
ECCP2/P2A⁽⁴⁾
1
AD15⁽¹⁾
x
x
ECCP2⁽⁵⁾
0
O
DIG LATE<7> data output.
I
ST PORTE<7> data input; weak pull-up when REPU bit is set.
O
DIG External memory interface, Address/Data Bit 15 output.⁽²⁾
I
TTL External memory interface, Data Bit 15 input.⁽²⁾
O
DIG ECCP2 compare output and PWM output; takes priority over
port data.
1
P2A⁽⁵⁾
0
I
ST ECCP2 capture input.
O
DIG ECCP2 Enhanced PWM output, Channel A; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend:
Note 1:
2:
3:
4:
5:
6:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
EMB functions are implemented on 100-pin devices only.
External memory interface I/O takes priority over all other digital and PSP I/O.
Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin and 100-pin devices).
Unimplemented on 64-pin devices.
Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (80-pin and 100-pin devices in
Microcontroller mode).
Unimplemented on 64-pin and 80-pin devices.
TABLE 11-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PORTE
LATE
TRISE
LATA
Legend:
Note 1:
RE7⁽¹⁾
RE6⁽¹⁾
RE5
RE4
RE3
RE2
LATE7⁽¹⁾ LATE6⁽¹⁾ LATE5 LATE4 LATE3 LATE2
TRISE7⁽¹⁾ TRISE6⁽¹⁾ TRISE5 TRISE4 TRISE3 TRISE2
RDPU REPU LATA5 LATA4 LATA3 LATA2
— = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Unimplemented on 64-pin devices; read as ‘0’.
RE1
LATE1
TRISE1
LATA1
Bit 0
RE0
LATE0
TRISE0
LATA0
Reset
Values
on Page:
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 2011 Microchip Technology Inc.
DS39762F-page 159