PIC18F97J60_11 Datasheet, PDF (158/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 11-11: PORTE FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RE0/AD8/RD/
RE0
P2D
0
O
DIG LATE<0> data output.
1
I
ST PORTE<0> data input; weak pull-up when REPU bit is set.
AD8⁽¹⁾
x
O
DIG External memory interface, Address/Data Bit 8 output.⁽²⁾
x
I
TTL External memory interface, Data bit 8 input.⁽²⁾
RD⁽⁶⁾
1
I
TTL Parallel Slave Port read enable control input.
P2D
0
O
DIG ECCP2 Enhanced PWM output, Channel D; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE1/AD9/WR/
RE1
P2C
0
O
DIG LATE<1> data output.
1
I
ST PORTE<1> data input; weak pull-up when REPU bit is set.
AD9⁽¹⁾
x
O
DIG External memory interface, Address/Data Bit 9 output.⁽²⁾
x
I
TTL External memory interface, Data Bit 9 input.⁽²⁾
WR⁽⁶⁾
1
I
TTL Parallel Slave Port write enable control input.
P2C
0
O
DIG ECCP2 Enhanced PWM output, Channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE2/AD10/CS/
RE2
0
P2B
1
AD10⁽¹⁾
x
x
CS⁽⁶⁾
1
P2B
0
O
DIG LATE<2> data output.
I
ST PORTE<2> data input; weak pull-up when REPU bit is set.
O
DIG External memory interface, Address/Data Bit 10 output.⁽²⁾
I
TTL External memory interface, Data Bit 10 input.⁽²⁾
I
TTL Parallel Slave Port chip select control input.
O
DIG ECCP2 Enhanced PWM output, Channel B; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE3/AD11/
P3C
RE3
0
1
AD11⁽¹⁾
x
x
P3C⁽³⁾
0
O
DIG LATE<3> data output.
I
ST PORTE<3> data input; weak pull-up when REPU bit is set.
O
DIG External memory interface, Address/Data Bit 11 output.⁽²⁾
I
TTL External memory interface, Data Bit 11 input.⁽²⁾
O
DIG ECCP3 Enhanced PWM output, Channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE4/AD12/
RE4
0
P3B
1
AD12⁽¹⁾
x
x
P3B⁽³⁾
0
O
DIG LATE<4> data output.
I
ST PORTE<4> data input; weak pull-up when REPU bit is set.
O
DIG External memory interface, Address/Data Bit 12 output.⁽²⁾
I
TTL External memory interface, Data Bit 12 input.⁽²⁾
O
DIG ECCP3 Enhanced PWM output, channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend:
Note 1:
2:
3:
4:
5:
6:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
EMB functions are implemented on 100-pin devices only.
External memory interface I/O takes priority over all other digital and PSP I/O.
Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin and 100-pin devices).
Unimplemented on 64-pin devices.
Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (80-pin and 100-pin devices in
Microcontroller mode).
Unimplemented on 64-pin and 80-pin devices.
DS39762F-page 158
 2011 Microchip Technology Inc.