PIC18F97J60_11 Datasheet, PDF (326/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
FIGURE 21-3:
EUSARTx TRANSMIT BLOCK DIAGRAM
TXxIE
TXxIF
MSb
(8)
Interrupt
TXEN Baud Rate CLK
Data Bus
TXREGx Register
8
LSb

0
TSR Register
BRG16
SPBRGHx SPBRGx
Baud Rate Generator
TX9
TX9D
Pin Buffer
and Control
TXx pin
TRMT SPEN TXCKP
FIGURE 21-4:
Write to TXREGx
BRG Output
(Shift Clock)
TXx (pin)
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION, TXCKP = 0 (TXx NOT INVERTED)
Word 1
Start bit
bit 0
1 TCY
bit 1
Word 1
bit 7/8 Stop bit
Word 1
Transmit Shift Reg
FIGURE 21-5:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK), TXCKP = 0
(TXx NOT INVERTED)
Write to TXREGx
BRG Output
(Shift Clock)
TXx (pin)
TXxIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
1 TCY
Start bit
bit 0
Word 1
Transmit Shift Reg.
1 TCY
bit 1
Word 1
bit 7/8
Stop bit
Start bit
bit 0
Word 2
Word 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
DS39762F-page 326
 2011 Microchip Technology Inc.