PIC18F97J60_11 Datasheet, PDF (33/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number _{Pin Buffer}
TQFP
Type Type
Description
MCLR
OSC1/CLKI
OSC1
CLKI
OSC2/CLKO
OSC2
CLKO
RA0/LEDA/AN0
RA0
LEDA
AN0
13
I
ST Master Clear (Reset) input. This pin is an active-low Reset to
the device.
63
Oscillator crystal or external clock input.
I
ST
Oscillator crystal input or external clock source input.
ST buffer when configured in internal RC mode; CMOS
otherwise.
I CMOS External clock source input. Always associated with
pin function, OSC1. (See related OSC2/CLKO pin.)
64
Oscillator crystal or clock output.
O
—
Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
O
—
In Internal RC mode, OSC2 pin outputs CLKO which has 1/4
the frequency of OSC1 and denotes the instruction cycle rate.
PORTA is a bidirectional I/O port.
35
I/O
TTL
Digital I/O.
O
—
Ethernet LEDA indicator output.
I Analog Analog Input 0.
RA1/LEDB/AN1
RA1
LEDB
AN1
34
I/O
TTL
Digital I/O.
O
—
Ethernet LEDB indicator output.
I Analog Analog Input 1.
RA2/AN2/VREF-
RA2
AN2
VREF-
33
I/O
TTL
Digital I/O.
I Analog Analog Input 2.
I Analog A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
RA4/T0CKI
RA4
T0CKI
32
I/O
TTL
Digital I/O.
I Analog Analog Input 3.
I Analog A/D reference voltage (high) input.
42
I/O
ST
Digital I/O.
I
ST
Timer0 external clock input.
RA5/AN4
RA5
AN4
Legend:
Note 1:
2:
3:
4:
5:
41
I/O
TTL
Digital I/O.
I Analog Analog Input 4.
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
OD
= Open-Drain (no P diode to VDD)
Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
 2011 Microchip Technology Inc.
DS39762F-page 33