PIC18F97J60_11 Datasheet, PDF (95/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 6-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values on Details on
POR, BOR Page:
ESTAT
—
BUFER
—
r
—
RXBUSY TXABRT PHYRDY -0-0 -000 73, 228
EIE
—
PKTIE
DMAIE
LINKIE
TXIE
—
TXERIE
RXERIE -000 0-00 73, 240
EDMACSH DMA Checksum Register High Byte
0000 0000 73, 265
EDMACSL DMA Checksum Register Low Byte
0000 0000 73, 265
EDMADSTH
—
—
—
DMA Destination Register High Byte
---0 0000 73, 265
EDMADSTL DMA Destination Register Low Byte
0000 0000 73, 265
EDMANDH
—
—
—
DMA End Register High Byte
---0 0000 73, 265
EDMANDL DMA End Register Low Byte
0000 0000 73, 265
EDMASTH
—
—
—
DMA Start Register High Byte
---0 0000 73, 265
EDMASTL DMA Start Register Low Byte
0000 0000 73, 265
ERXWRPTH
—
—
—
Receive Buffer Write Pointer High Byte
---0 0000 73, 225
ERXWRPTL Receive Buffer Write Pointer Low Byte
0000 0000 73, 225
ERXRDPTH
—
—
—
Receive Buffer Read Pointer High Byte
---0 0101 73, 225
ERXRDPTL Receive Buffer Read Pointer Low Byte
1111 1010 73, 225
ERXNDH
—
—
—
Receive End Register High Byte
---1 1111 73, 225
ERXNDL
Receive End Register Low Byte
1111 1111 73, 225
ERXSTH
—
—
—
Receive Start Register High Byte
---0 0101 73, 225
ERXSTL
Receive Start Register Low Byte
1111 1010 73, 225
ETXNDH
—
—
—
Transmit End Register High Byte
---0 0000 74, 226
ETXNDL
Transmit End Register Low Byte
0000 0000 74, 226
ETXSTH
—
—
—
Transmit Start Register High Byte
---0 0000 74, 226
ETXSTL
Transmit Start Register Low Byte
0000 0000 74, 226
EWRPTH
—
—
—
Buffer Write Pointer High Byte
---0 0000 74, 223
EWRPTL Buffer Write Pointer Low Byte
0000 0000 74, 223
EPKTCNT Ethernet Packet Count Register
0000 0000 74, 252
ERXFCON
UCEN
ANDOR
CRCEN
PMEN
MPEN
HTEN
MCEN
BCEN 1010 0001 74, 260
EPMOH
—
—
—
Pattern Match Offset Register High Byte
---0 0000 74, 263
EPMOL
Pattern Match Offset Register Low Byte
0000 0000 74, 263
EPMCSH Pattern Match Checksum Register High Byte
0000 0000 74, 263
EPMCSL
Pattern Match Checksum Register Low Byte
0000 0000 74, 263
EPMM7
Pattern Match Mask Register Byte 7
0000 0000 74, 263
EPMM6
Pattern Match Mask Register Byte 6
0000 0000 74, 263
EPMM5
Pattern Match Mask Register Byte 5
0000 0000 74, 263
EPMM4
Pattern Match Mask Register Byte 4
0000 0000 74, 263
EPMM3
Pattern Match Mask Register Byte 3
0000 0000 74, 263
EPMM2
Pattern Match Mask Register Byte 2
0000 0000 74, 263
EPMM1
Pattern Match Mask Register Byte 1
0000 0000 74, 263
EPMM0
Pattern Match Mask Register Byte 0
0000 0000 74, 263
Legend: x = unknown; u = unchanged; - = unimplemented, read as ‘0’; q = value depends on condition; r = reserved bit, do not modify. Shaded cells
are unimplemented, read as ‘0’.
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
2: Bit 21 of the PC is only available in Serial Programming modes.
3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
4: Alternate names and definitions for these bits when the MSSP module is operating in I²C™ Slave mode.
5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown
apply only to 100-pin devices.
6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as ‘0’. Reset
values are shown for 100-pin devices.
7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’.
8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’.
9: Implemented in 100-pin devices in Microcontroller mode only.
 2011 Microchip Technology Inc.
DS39762F-page 95