PIC18F97J60_11 Datasheet, PDF (356/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
FIGURE 24-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+
CVRSS = 1
VDD
CVRSS = 0
8R
CVREN
R
R
R
R
16 Steps
CVR<3:0>
CVREF
R
R
R
CVRR
VREF-
8R
CVRSS = 1
CVRSS = 0
24.2 Comparator Voltage Reference
Accuracy/Error
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 24-1) keep CVREF from approaching the refer-
ence source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 28.0 “Electrical Characteristics”.
24.3 Operation During Sleep
When the device wakes up from Sleep through an
interrupt, or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
24.4 Effects of a Reset
A device Reset disables the voltage reference by
clearing bit, CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
bit, CVROE (CVRCON<6>), and selects the
high-voltage range by clearing bit, CVRR
(CVRCON<5>). The CVR value select bits are also
cleared.
24.5 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RF5 pin if the
CVROE bit is set. Enabling the voltage reference out-
put onto RA2, when it is configured as a digital input,
will increase current consumption. Connecting RF5 as
a digital output with CVRSS enabled will also increase
current consumption.
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to VREF.
Figure 24-2 shows an example buffering technique.
DS39762F-page 356
 2011 Microchip Technology Inc.