PIC18F97J60_11 Datasheet, PDF (302/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
20.4.8
I²C MASTER MODE START
CONDITION TIMING
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPxCON2<0>). If the SDAx and
SCLx pins are sampled high, the Baud Rate Generator
is reloaded with the contents of SSPxADD<6:0> and
starts its count. If SCLx and SDAx are both sampled
high when the Baud Rate Generator times out (TBRG),
the SDAx pin is driven low. The action of the SDAx
being driven low while SCLx is high is the Start condi-
tion and causes the S bit (SSPxSTAT<3>) to be set.
Following this, the Baud Rate Generator is reloaded
with the contents of SSPxADD<6:0> and resumes its
count. When the Baud Rate Generator times out
(TBRG), the SEN bit (SSPxCON2<0>) will be auto-
matically cleared by hardware. The Baud Rate
Generator is suspended, leaving the SDAx line held
low and the Start condition is complete.
Note:
If, at the beginning of the Start condition,
the SDAx and SCLx pins are already sam-
pled low, or if during the Start condition,
the SCLx line is sampled low before the
SDAx line is driven low, a bus collision
occurs. The Bus Collision Interrupt Flag,
BCLxIF, is set, the Start condition is
aborted and the I²C module is reset into its
Idle state.
20.4.8.1 WCOL Status Flag
If the user writes the SSPxBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPxCON2 is disabled until the Start
condition is complete.
FIGURE 20-21: FIRST START BIT TIMING
Write to SEN bit occurs here
Set S bit (SSPxSTAT<3>)
SDAx = 1,
SCLx = 1
At completion of Start bit,
hardware clears SEN bit
and sets SSPxIF bit
TBRG
TBRG
Write to SSPxBUF occurs here
SDAx
1st bit
TBRG
2nd bit
SCLx
TBRG
S
DS39762F-page 302
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