PIC18F97J60_11 Datasheet, PDF (255/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 19-6: SUMMARY OF REGISTERS ASSOCIATED WITH PACKET TRANSMISSION
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
Page:
EIE
EIR
ESTAT
—
PKTIE DMAIE LINKIE
TXIE
—
TXERIE RXERIE
73
—
PKTIF DMAIF LINKIF
TXIF
—
TXERIF RXERIF
73
—
BUFER
—
r
—
RXBUSY TXABRT PHYRDY
73
ECON1
TXRST RXRST DMAST CSUMEN TXRTS
RXEN
—
—
70
ETXSTL Transmit Start Register Low Byte (ETXST<7:0>)
74
ETXSTH
—
—
— Transmit Start Register High Byte (ETXST<12:8>)
74
ETXNDL Transmit End Register Low Byte (ETXND<7:0>)
74
ETXNDH
—
—
— Transmit End Register High Byte (ETXND<12:8>)
74
MACON1
—
—
—
r
TXPAUS RXPAUS PASSALL MARXEN
75
MACON3 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX
75
MACON4
—
DEFER
r
r
—
—
r
r
75
MABBIPG
—
BBIPG6 BBIPG5 BBIPG4 BBIPG3 BBIPG2 BBIPG1 BBIPG0
75
MAIPGL
— MAC Non Back-to-Back Inter-Packet Gap Register Low Byte (MAIPGL<6:0>)
75
MAIPGH
— MAC Non Back-to-Back Inter-Packet Gap Register High Byte (MAIPGH<6:0>)
75
MAMXFLL Maximum Frame Length Register Low Byte (MAMXFL<7:0>)
74
MAMXFLH Maximum Frame Length Register High Byte (MAMXFL<15:8>)
74
Legend: — = unimplemented, r = reserved bit. Shaded cells are not used.
TABLE 19-7: SUMMARY OF REGISTERS ASSOCIATED WITH PACKET RECEPTION
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EIE
—
PKTIE DMAIE LINKIE
TXIE
—
TXERIE RXERIE
EIR
—
PKTIF
DMAIF
LINKIF
TXIF
—
TXERIF RXERIF
ESTAT
—
BUFER
—
r
—
RXBUSY TXABRT PHYRDY
ECON2
AUTOINC PKTDEC ETHEN
—
—
—
—
—
ECON1
TXRST RXRST DMAST CSUMEN TXRTS RXEN
—
—
ERXSTL Receive Start Register Low Byte (ERXST<7:0>)
ERXSTH
—
—
— Receive Start Register High Byte (ERXST<12:8>)
ERXNDL Receive End Register Low Byte (ERXND<7:0>)
ERXNDH
—
—
— Receive End Register High Byte (ERXND<12:8>)
ERXRDPTL Receive Buffer Read Pointer Low Byte (ERXRDPT<7:0>)
ERXRDPTH
—
—
— Receive Buffer Read Pointer High Byte (ERXRDPT<12:8>)
ERXFCON UCEN ANDOR CRCEN PMEN
MPEN
HTEN
MCEN
BCEN
EPKTCNT Ethernet Packet Count Register
MACON1
—
—
—
r
TXPAUS RXPAUS PASSALL MARXEN
MACON3 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX
MAMXFLL Maximum Frame Length Register Low Byte (MAMXFL<7:0>)
MAMXFLH Maximum Frame Length Register High Byte (MAMXFL<15:8>)
Legend: — = unimplemented, r = reserved bit. Shaded cells are not used.
Reset
Values on
Page:
73
73
73
73
70
74
74
74
74
73
73
74
74
75
75
74
74
 2011 Microchip Technology Inc.
DS39762F-page 255