PIC18F97J60_11 Datasheet, PDF (232/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
REGISTER 19-8: MISTAT: MII STATUS REGISTER
U-0
—
bit 7
U-0
U-0
U-0
R-0
—
—
—
r
R-0
NVALID
R-0
SCAN
R-0
BUSY
bit 0
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
Reserved: Do not use
NVALID: MII Management Read Data Not Valid bit
1 = The contents of the MIRD registers are not valid yet
0 = The MII Management read cycle has completed and the MIRD registers have been updated
SCAN: MII Management Scan Operation bit
1 = MII Management scan operation is in progress
0 = No MII Management scan operation is in progress
BUSY: MII Management Busy bit
1 = A PHY register is currently being read, or written to. For internal synchronization, the hardware
will delay setting this bit for two TCY following a firmware command, which sets the MIISCAN or
MIIRD bits, or writes to the MIWRH register.
0 = The MII Management interface is Idle
19.2.5 PHY REGISTERS
The PHY registers provide configuration and control of
the PHY module, as well as status information about its
operation. All PHY registers are 16 bits in width.
PHY registers are accessed with a 5-bit address, for a
total of 32 possible registers; of these, only 7 addresses
are implemented. The implemented registers are listed
in Table 19-3. The main PHY Control registers are
described in Register 19-9 through Register 19-13. The
other PHY Control and Status registers are described
later in this chapter.
Unimplemented registers must never be written to.
Reading these locations will return indeterminate data.
Within implemented registers, all reserved bit locations
that are listed as writable must always be written with
the value provided in the register description. When
read, these reserved bits can be ignored.
Thy PHY registers are only accessible through the MII
Management interface. They must not be read or
written to until the PHY start-up timer has expired and
the PHYRDY bit (ESTAT<0>) is set.
19.2.5.1 PHSTAT Registers
The PHSTAT1 and PHSTAT2 registers contain
read-only bits that show the current status of the PHY
module’s operations, particularly the conditions of the
communications link to the rest of the network.
The PHSTAT1 register (Register 19-10) contains the
LLSTAT bit. The bit clears and latches low if the physical
layer link has gone down since the last read of the
register. The application can periodically poll LLSTAT to
determine exactly when the link fails. It may be
particularly useful if the link change interrupt is not used.
The PHSTAT2 register (Register 19-12) contains status
bits which report if the PHY module is linked to the
network and whether or not it is transmitting or receiving.
19.2.5.2 Accessing PHY Registers
As already mentioned, the PHY registers exist in a
different memory space and are not directly accessible
by the microcontroller. Instead, they are addressed
through a special set of MII registers in the Ethernet
SFR bank that implement a Media Independent
Interface Management (MIIM).
Access is similar to that of the Ethernet buffer, but uses
separate read and write buffers (MIRDH:MIRDL and
MIWRH:MIWRL) and a 5-bit address register
(MIREGADR). In addition, the MICMD and MISTAT
registers are used to control read and write operations.
DS39762F-page 232
 2011 Microchip Technology Inc.