PIC18F97J60_11 Datasheet, PDF (137/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
10.3 PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2, PIE3). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 10-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
PSPIE⁽¹⁾
bit 7
R/W-0
ADIE
R/W-0
RC1IE
R/W-0
TX1IE
R/W-0
SSP1IE
R/W-0
CCP1IE
R/W-0
TMR2IE
R/W-0
TMR1IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit⁽¹⁾
1 = Enabled
0 = Disabled
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5
RC1IE: EUSART1 Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4
TX1IE: EUSART1 Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3
SSP1IE: MSSP1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2
CCP1IE: ECCP1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
Note 1: Implemented in 100-pin devices in Microcontroller mode only.
 2011 Microchip Technology Inc.
DS39762F-page 137