PIC18F97J60_11 Datasheet, PDF (236/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
REGISTER 19-11: PHCON2: PHY CONTROL REGISTER 2
U-0
—
bit 15
R/W-0
FRCLNK
R/W-0
r
R/W-0
r
R/W-0
r
R/W-0
r
R/W-0
r
R/W-0
HDLDIS
bit 8
R/W-0
r
bit 7
R/W-0
r
R/W-0
r
R/W-0
RXAPDIS
R/W-0
r
R/W-0
r
R/W-0
r
R/W-0
r
bit 0
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13-9
bit 8
bit 7-5
bit 4
bit 3-0
Unimplemented: Read as ‘0’
FRCLNK: PHY Force Linkup bit
1 = Force linkup even when no link partner is detected (transmission is always allowed)
0 = Normal operation (PHY blocks transmission attempts unless a link partner is attached)
Reserved: Write as ‘0’
HDLDIS: PHY Half-Duplex Loopback Disable bit
1 = Normal PHY operation
0 = Reserved
Reserved: Write as ‘0’
RXAPDIS: RX+/RX- Operating mode bit
1 = Normal operation
0 = Reserved
Reserved: Write as ‘0’
Note: Improper Ethernet operation may result if HDLDIS or RXAPDIS is cleared, which is the Reset default.
Always initialize these bits set before using the Ethernet module.
DS39762F-page 236
 2011 Microchip Technology Inc.