PIC18F97J60_11 Datasheet, PDF (24/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTG is a bidirectional I/O port.
RG4/CCP5/P1D
RG4
CCP5
P1D
8
I/O
ST
Digital I/O.
I/O
ST
Capture 5 input/Compare 5 output/PWM5 output.
O
—
ECCP1 PWM Output D.
VSS
9, 25, 41, 56 P
— Ground reference for logic and I/O pins.
VDD
26, 38, 57
P
— Positive supply for peripheral digital logic and I/O pins.
AVSS
20
P
— Ground reference for analog modules.
AVDD
19
P
— Positive supply for analog modules.
ENVREG
18
I
ST Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
VCAP
10
Core logic power or external filter capacitor connection.
P
—
Positive supply for microcontroller core logic
(regulator disabled).
P
—
External filter capacitor connection (regulator enabled).
VSSPLL
55
P
— Ground reference for Ethernet PHY PLL.
VDDPLL
54
P
— Positive 3.3V supply for Ethernet PHY PLL.
VSSTX
52
P
— Ground reference for Ethernet PHY transmit subsystem.
VDDTX
49
P
— Positive 3.3V supply for Ethernet PHY transmit subsystem.
VSSRX
45
P
— Ground reference for Ethernet PHY receive subsystem.
VDDRX
48
P
— Positive 3.3V supply for Ethernet PHY receive subsystem.
RBIAS
53
I
Analog Bias current for Ethernet PHY. Must be tied to VSS via a resistor;
see Section 19.0 “Ethernet Module” for specification.
TPOUT+
51
O
— Ethernet differential signal output.
TPOUT-
50
O
— Ethernet differential signal output.
TPIN+
47
I
Analog Ethernet differential signal input.
TPIN-
46
I
Analog Ethernet differential signal input.
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
I = Input
P = Power
CMOS
Analog
O
OD
= CMOS compatible input or output
= Analog input
= Output
= Open-Drain (no P diode to VDD)
DS39762F-page 24
 2011 Microchip Technology Inc.