PIC18F97J60_11 Datasheet, PDF (130/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
FIGURE 10-1:
PIC18F97J60 FAMILY INTERRUPT LOGIC
PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
PIR2<7:5,3,1:0>
PIE2<7:5,3,1:0>
IPR2<7:5,3,1:0>
PIR3<7:0>
PIE3<7:0>
IPR3<7:0>
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
PIR2<7:5,3,1:0>
PIE2<7:5,3,1:0>
IPR2<7:5,3,1:0>
PIR3<7:0>
PIE3<7:0>
IPR3<7:0>
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
IPEN
IPEN
PEIE/GIEL
IPEN
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
Wake-up if in
Idle or Sleep modes
Interrupt to CPU
Vector to Location
0008h
GIE/GIEH
IPEN
Interrupt to CPU
Vector to Location
0018h
GIE/GIEH
PEIE/GIEL
DS39762F-page 130
 2011 Microchip Technology Inc.