PIC18F97J60_11 Datasheet, PDF (367/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
25.2 Watchdog Timer (WDT)
For PIC18F97J60 family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexor, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from 4 ms to 131.072 seconds (2.18 minutes). The
WDT and postscaler are cleared whenever a SLEEP or
CLRWDT instruction is executed, or a clock failure
(primary or Timer1 oscillator) has occurred.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
25.2.1 CONTROL REGISTER
The WDTCON register (Register 25-9) is a readable
and writable register. The SWDTEN bit enables or dis-
ables WDT operation. This allows software to override
the WDTEN Configuration bit and enable the WDT only
if it has been disabled by the Configuration bit.
FIGURE 25-1:
WDT BLOCK DIAGRAM
SWDTEN
INTRC Oscillator
CLRWDT
All Device Resets
WDTPS<3:0>
Sleep
Enable WDT
INTRC Control
WDT Counter
128
Programmable Postscaler ^Reset
1:1 to 1:32,768
WDT
4
Wake-up from
Power-Managed
Modes
WDT
Reset
 2011 Microchip Technology Inc.
DS39762F-page 367