PIC18F97J60_11 Datasheet, PDF (460/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 28-23: MASTER SSP I²C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) —
ms
400 kHz mode 2(TOSC)(BRG + 1) —
ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) —
ms
400 kHz mode 2(TOSC)(BRG + 1) —
ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
102 TR
SDAx and SCLx 100 kHz mode
Rise Time
400 kHz mode
—
20 + 0.1 CB
1000
300
ns CB is specified to be from
ns ^{10 to 400 pF}
1 MHz mode⁽¹⁾
—
300 ns
103 TF
SDAx and SCLx 100 kHz mode
Fall Time
400 kHz mode
—
20 + 0.1 CB
300 ns CB is specified to be from
300 ns ^{10 to 400 pF}
1 MHz mode⁽¹⁾
—
100 ns
90
TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) —
ms Only relevant for
Setup Time
400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms ^{Repeated Start}
ms ^condition
91
THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) —
ms After this period, the first
Hold Time
400 kHz mode 2(TOSC)(BRG + 1) —
ms ^{clock pulse is generated}
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
106 THD:DAT Data Input
100 kHz mode
0
—
ns
Hold Time
400 kHz mode
0
0.9 ms
1 MHz mode⁽¹⁾
TBD
—
ns
107 TSU:DAT Data Input
100 kHz mode
250
Setup Time
400 kHz mode
100
—
ns (Note 2)
—
ns
1 MHz mode⁽¹⁾
TBD
—
ns
92
TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) —
ms
Setup Time
400 kHz mode 2(TOSC)(BRG + 1) —
ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
109 TAA
Output Valid
from Clock
100 kHz mode
400 kHz mode
—
3500 ns
—
1000 ns
1 MHz mode⁽¹⁾
—
—
ns
110 TBUF Bus Free Time 100 kHz mode
400 kHz mode
1 MHz mode⁽¹⁾
4.7
1.3
TBD
— ms Time the bus must be free
—
ms ^{before a new transmission}
—
ms ^{can start}
D102 CB
Bus Capacitive Loading
—
400 pF
Legend:
Note 1:
2:
TBD = To Be Determined
Maximum pin capacitance = 10 pF for all I²C™ pins.
A Fast mode I²C bus device can be used in a Standard mode I²C bus system, but Parameter #107  250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data
bit to the SDAx line, Parameter #102 + Parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before
the SCLx line is released.
DS39762F-page 460
 2011 Microchip Technology Inc.