PIC18F97J60_11 Datasheet, PDF (450/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
FIGURE 28-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
I/O pins
33
32
30
31
34
34
Note: Refer to Figure 28-3 for load conditions.
TABLE 28-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min Typ Max Units
Conditions
30
TMCL MCLR Pulse Width (low)
2
—
—
s
31
TWDT Watchdog Timer Time-out Period
2.8
4.1
5.4
ms
(no postscaler)
32
TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period
33
TPWRT Power-up Timer Period
46.2
66
85.8
ms
34
TIOZ I/O High-Impedance from MCLR
—
— 3TCY + 2 s System clock available
Low or Watchdog Timer Reset
—
—
415
s System clock unavailable
(Sleep mode or
primary oscillator off)
38
TCSD CPU Start-up Time
—
200
—
s
DS39762F-page 450
 2011 Microchip Technology Inc.