PIC18F97J60_11 Datasheet, PDF (156/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 11-9: PORTD FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RD5/AD5/
RD5⁽¹⁾
0
O
DIG LATD<5> data output.
PSP5/SDI2/
SDA2⁽¹⁾
AD5⁽¹⁾
1
x
I
ST PORTD<5> data input; weak pull-up when RDPU bit is set.
O
DIG External memory interface, Address/Data Bit 5 output.⁽²⁾
x
I
TTL External memory interface, Data Bit 5 input.⁽²⁾
PSP5⁽¹⁾
x
O
DIG PSP read output data (LATD<5>); takes priority over port data.
x
I
TTL PSP write data input.
SDI2⁽¹⁾
1
SDA2⁽¹⁾
1
1
I
ST SPI data input (MSSP2 module).
O
DIG I²C™ data output (MSSP2 module); takes priority over port data.
I
ST I²C data input (MSSP2 module); input type depends on module
setting.
RD6/AD6/
RD6⁽¹⁾
0
O
DIG LATD<6> data output.
PSP6/SCK2/
SCL2⁽¹⁾
AD6⁽¹⁾
1
x
I
ST PORTD<6> data input; weak pull-up when RDPU bit is set.
O DIG-3 External memory interface, Address/Data Bit 6 output.⁽²⁾
x
I
TTL External memory interface, Data Bit 6 input.⁽²⁾
PSP6⁽¹⁾
x
O
DIG PSP read output data (LATD<6>); takes priority over port data.
x
I
TTL PSP write data input.
SCK2⁽¹⁾
0
O
DIG SPI clock output (MSSP2 module); takes priority over port data.
1
SCL2⁽¹⁾
0
1
I
ST SPI clock input (MSSP2 module).
O
DIG I²C clock output (MSSP2 module); takes priority over port data.
I
ST I²C clock input (MSSP2 module); input type depends on module
setting.
RD7/AD7/
RD7⁽¹⁾
0
O
DIG LATD<7> data output.
PSP7/SS2⁽¹⁾
1
I
ST PORTD<7> data input; weak pull-up when RDPU bit is set.
AD7⁽¹⁾
x
O
DIG External memory interface, Address/Data Bit 7 output.⁽²⁾
x
I
TTL External memory interface, Data Bit 7 input.⁽²⁾
PSP7⁽¹⁾
x
O
DIG PSP read output data (LATD<7>); takes priority over port data.
x
I
TTL PSP write data input.
SS2⁽¹⁾
x
I
TTL Slave select input for MSSP2 module.
Legend:
Note 1:
2:
3:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
These features or port pins are implemented only on 100-pin devices.
External memory interface I/O takes priority over all other digital and PSP I/O.
These features are implemented on this pin only on 64-pin devices; for all other devices, they are multiplexed with
RE6/RH7 (P1B), RG0 (ECCP3/P3A) or RG3 (CCP4/P3D).
TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PORTD
LATD
TRISD
LATA
Legend:
Note 1:
RD7⁽¹⁾
RD6⁽¹⁾
RD5⁽¹⁾
RD4⁽¹⁾
RD3⁽¹⁾
LATD7⁽¹⁾ LATD6⁽¹⁾ LATD5⁽¹⁾ LATD4⁽¹⁾ LATD3⁽¹⁾
TRISD7⁽¹⁾ TRISD6⁽¹⁾ TRISD5⁽¹⁾ TRISD4⁽¹⁾ TRISD3⁽¹⁾
RDPU REPU LATA5 LATA4 LATA3
Shaded cells are not used by PORTD.
Unimplemented on 64-pin and 80-pin devices; read as ‘0’.
RD2
LATD2
TRISD2
LATA2
RD1
LATD1
TRISD1
LATA1
Bit 0
RD0
LATD0
TRISD0
LATA0
Reset
Values
on Page:
72
72
71
72
DS39762F-page 156
 2011 Microchip Technology Inc.