PIC18F97J60_11 Datasheet, PDF (447/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
FIGURE 28-5:
OSC1
CLKO AND I/O TIMING
Q4
Q1
10
CLKO
13 ₁₄
I/O pin
(Input)
17
I/O pin
(Output)
Old Value
20, 21
Note: Refer to Figure 28-3 for load conditions.
Q2
Q3
11
12
19
18
16
15
New Value
TABLE 28-9: CLKO AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ
Max Units Conditions
10
TOSH2CKL OSC1  to CLKO 
—
75
200
ns
11
TOSH2CKH OSC1  to CLKO 
—
75
200
ns
12
TCKR
CLKO Rise Time
—
15
30
ns
13
TCKF
CLKO Fall Time
—
15
30
ns
14
TCKL2IOV CLKO  to Port Out Valid
—
— 0.5 TCY + 20 ns
15
TIOV2CKH Port In Valid before CLKO 
0.25 TCY + 25 —
—
ns
16
TCKH2IOI Port In Hold after CLKO 
0
—
—
ns
17
TOSH2IOV OSC1  (Q1 cycle) to Port Out Valid
—
50
150
ns
18
TOSH2IOI OSC1  (Q2 cycle) to Port Input Invalid
(I/O in hold time)
100
—
—
ns
19
TIOV2OSH Port Input Valid to OSC1 
(I/O in setup time)
0
—
—
ns
20
TIOR
Port Output Rise Time
—
—
6
ns
21
TIOF
Port Output Fall Time
—
—
5
ns
22† TINP
INTx pin High or Low Time
TCY
—
—
ns
23† TRBP
RB<7:4> Change INTx High or Low Time
TCY
—
—
ns
† These parameters are asynchronous events not related to any internal clock edges.
 2011 Microchip Technology Inc.
DS39762F-page 447