PIC18F97J60_11 Datasheet, PDF (485/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
ECON1 (Ethernet Control 1) .................................... 227
ECON2 (Ethernet Control 2) .................................... 228
EECON1 (EEPROM Control 1) ................................ 107
EFLOCON (Ethernet Flow Control) ......................... 258
EIE (Ethernet Interrupt Enable) ................................ 240
EIR (Ethernet Interrupt Request, Flag) .................... 241
ERXFCON (Ethernet Receive Filter Control) ........... 260
ESTAT (Ethernet Status) ......................................... 228
INTCON (Interrupt Control) ...................................... 131
INTCON2 (Interrupt Control 2) ................................. 132
INTCON3 (Interrupt Control 3) ................................. 133
IPR1 (Peripheral Interrupt Priority 1) ........................ 140
IPR2 (Peripheral Interrupt Priority 2) ........................ 141
IPR3 (Peripheral Interrupt Priority 3) ........................ 142
MABBIPG (MAC Back-to-Back
Inter-Packet Gap) ............................................ 246
MACON1 (MAC Control 1) ....................................... 229
MACON3 (MAC Control 3) ....................................... 230
MACON4 (MAC Control 4) ....................................... 231
MEMCON (External Memory Bus Control) .............. 116
MICMD (MII Command) ........................................... 231
MISTAT (MII Status) ................................................ 232
OSCCON (Oscillator Control) .................................... 53
OSCTUNE (PLL Block Control) ................................. 51
PHCON1 (PHY Control 1) ........................................ 235
PHCON2 (PHY Control 2) ........................................ 236
PHIE (PHY Interrupt Enable) ................................... 242
PHIR (PHY Interrupt Request, Flag) ........................ 242
PHLCON (PHY Module LED Control) ...................... 238
PHSTAT1 (Physical Layer Status 1) ........................ 235
PHSTAT2 (Physical Layer Status 2) ........................ 237
PIE1 (Peripheral Interrupt Enable 1) ........................ 137
PIE2 (Peripheral Interrupt Enable 2) ........................ 138
PIE3 (Peripheral Interrupt Enable 3) ........................ 139
PIR1 (Peripheral Interrupt Request (Flag) 1) ........... 134
PIR2 (Peripheral Interrupt Request (Flag) 2) ........... 135
PIR3 (Peripheral Interrupt Request (Flag) 3) ........... 136
PSPCON (Parallel Slave Port Control) .................... 169
RCON (Reset Control) ....................................... 64, 143
RCSTAx (Receive Status and Control x) ................. 317
SSPxCON1 (MSSPx Control 1, I²C Mode) .............. 281
SSPxCON1 (MSSPx Control 1, SPI Mode) ............. 271
SSPxCON2 (MSSPx Control 2,
I²C Master Mode) ............................................ 282
SSPxCON2 (MSSPx Control 2,
I²C Slave Mode) .............................................. 283
SSPxSTAT (MSSPx Status, I²C Mode) ................... 280
SSPxSTAT (MSSPx Status, SPI Mode) .................. 270
STATUS ..................................................................... 97
STKPTR (Stack Pointer) ............................................ 82
T0CON (Timer0 Control) .......................................... 171
T1CON (Timer1 Control) .......................................... 175
T2CON (Timer2 Control) .......................................... 180
T3CON (Timer3 Control) .......................................... 183
T4CON (Timer4 Control) .......................................... 187
TXSTAx (Transmit Status and Control x) ................. 316
WDTCON (Watchdog Timer Control) ...................... 368
RESET ............................................................................. 405
Reset ................................................................................. 63
Brown-out Reset (BOR) ............................................. 63
Configuration Mismatch (CM) .................................... 63
MCLR Reset, During Power-Managed Modes .......... 63
MCLR Reset, Normal Operation ................................ 63
Power-on Reset (POR) .............................................. 63
RESET Instruction ..................................................... 63
Stack Full Reset ........................................................ 63
Stack Underflow Reset .............................................. 63
State of Registers ...................................................... 68
Watchdog Timer (WDT) Reset
During Execution ............................................... 63
Resets ............................................................................. 359
Brown-out Reset (BOR) ........................................... 359
Oscillator Start-up Timer (OST) ............................... 359
Power-on Reset (POR) ............................................ 359
Power-up Timer (PWRT) ......................................... 359
Stack Full/Underflow .................................................. 83
RETFIE ............................................................................ 406
RETLW ............................................................................ 406
RETURN .......................................................................... 407
Return Address Stack ........................................................ 81
Return Stack Pointer (STKPTR) ........................................ 82
Revision History ............................................................... 475
RLCF ............................................................................... 407
RLNCF ............................................................................. 408
RRCF ............................................................................... 408
RRNCF ............................................................................ 409
S
SCKx ............................................................................... 269
SDIx ................................................................................. 269
SDOx ............................................................................... 269
SEC_IDLE Mode ............................................................... 60
SEC_RUN Mode ................................................................ 56
Serial Clock, SCKx .......................................................... 269
Serial Data In (SDIx) ........................................................ 269
Serial Data Out (SDOx) ................................................... 269
Serial Peripheral Interface. See SPI Mode.
SETF ............................................................................... 409
Slave Select (SSx) ........................................................... 269
SLEEP ............................................................................. 410
Sleep
OSC1 and OSC2 Pin States ...................................... 54
Software Simulator (MPLAB SIM) ................................... 427
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ........................................... 359
Special Function Registers
Ethernet SFRs ........................................................... 90
SPI Mode (MSSP)
Associated Registers ............................................... 278
Bus Mode Compatibility ........................................... 277
Clock Speed and Module Interactions ..................... 277
Effects of a Reset .................................................... 277
Enabling SPI I/O ...................................................... 273
Master Mode ............................................................ 274
Master/Slave Connection ........................................ 273
Operation ................................................................. 272
Operation in Power-Managed Modes ...................... 277
 2011 Microchip Technology Inc.
DS39762F-page 485