PIC18F97J60_11 Datasheet, PDF (231/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
REGISTER 19-6: MACON4: MAC CONTROL REGISTER 4
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R-0
R-0
—
DEFER
r
r
—
—
r
r
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5-4
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
DEFER: Defer Transmission Enable bit (applies to half duplex only)
1 = When the medium is occupied, the MAC waits indefinitely for it to become free when attempting to
transmit (use this setting for IEE 802.3 compliance)
0 = When the medium is occupied, the MAC aborts the transmission after the excessive deferral limit
is reached
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
REGISTER 19-7: MICMD: MII COMMAND REGISTER
U-0
—
bit 7
U-0
U-0
U-0
U-0
—
—
—
—
U-0
R/W-0
R/W-0
—
MIISCAN
MIIRD
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-2
bit 1
bit 0
Unimplemented: Read as ‘0’
MIISCAN: MII Scan Enable bit
1 = PHY register at MIREGADR is continuously read and the data is placed in the MIRD registers
0 = No MII Management scan operation is in progress
MIIRD: MII Read Enable bit
1 = PHY register at MIREGADR is read once and the data is placed in the MIRD registers
0 = No MII Management read operation is in progress
 2011 Microchip Technology Inc.
DS39762F-page 231