PIC18F97J60_11 Datasheet, PDF (122/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
8.6.4 16-BIT MODE TIMING
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 8-4 and Figure 8-5.
FIGURE 8-4:
EXTERNAL MEMORY BUS TIMING FOR TBLRD
(EXTENDED MICROCONTROLLER MODE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 _{Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4}
A<19:16>
AD<15:0>
CE
ALE
OE
Memory
Cycle
Instruction
Execution
Opcode Fetch
TBLRD*
from 000100h
INST(PC – 2)
0Ch
CF33h
9256h
Opcode Fetch
MOVLW 55h
from 000102h
TBLRD Cycle 1
TBLRD 92h
from 199E67h
TBLRD Cycle 2
Opcode Fetch
ADDLW 55h
from 000104h
MOVLW
FIGURE 8-5:
EXTERNAL MEMORY BUS TIMING FOR SLEEP
(EXTENDED MICROCONTROLLER MODE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
A<19:16>
AD<15:0>
CE
ALE
OE
Memory
Cycle
Instruction
Execution
00h
3AAAh
0003h
00h
3AABh
0E55h
Opcode Fetch
SLEEP
from 007554h
INST(PC – 2)
Opcode Fetch
MOVLW 55h
from 007556h
SLEEP
Sleep Mode, Bus Inactive
DS39762F-page 122
 2011 Microchip Technology Inc.