HD6475348R Datasheet, PDF (99/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Section 4 Exception Handling
4.1 Overview
4.1.1 Types of Exception Handling and Their Priority
As indicated in table 4-1 (a) and (b), exception handling can be initiated by a reset, address error,
trace, interrupt, or instruction. An instruction initiates exception handling if the instruction is an
invalid instruction, a trap instruction, or a DIVXU instruction with zero divisor. Exception
handling begins with a hardware exception-handling sequence which prepares for the execution of
a user-coded software exception-handling routine.
There is a priority order among the different types of exceptions, as shown in table 4-1 (a). If two
or more exceptions occur simultaneously, they are handled in their order of priority. An
instruction exception cannot occur simultaneously with other types of exceptions.
Table 4-1 (a) Exceptions and Their Priority
Exception
Priority Type
High Reset
Address error
Trace
Interrupt
Low
Source Detection Timing
External, RES Low-to-High transition
internal
Internal Instruction fetch or data
read/write bus cycle
Internal End of instruction execution,
if T = 1 in status register
External, End of instruction execution or
internal end of exception-handling
sequence
Start of Exception-
Handling Sequence
Immediately
End of instruction execution
End of instruction execution
End of instruction execution
Table 4-1 (b) Instruction Exceptions
Exception Type
Invalid instruction
Trap instruction
Zero divide
Start of Exception-Handling Sequence
Attempted execution of instruction with undefined code
Started by execution of trap instruction
Attempted execution of DIVXU instruction with zero divisor
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