HD6475348R Datasheet, PDF (277/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

14.2.7 Serial Status Register (SSR)—H'FEDC, H'FEF4
Bit
7
6
5
4
3
2
1
0
TDRE RDRF ORER FER PER
—
—
—
Initial value
1
0
0
0
0
1
1
1
Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* —
—
—
* Software can write a 0 to clear the flags, but cannot write a 1 in these bits.
The SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'87 at a
reset and in the standby modes.
Bit 7—Transmit Data Register Empty (TDRE): This bit indicates when the TDR contents have
been transferred to the TSR and the next character can safely be written in the TDR.
Bit 7
TDRE
0
1
Description
This bit is cleared from 1 to 0 when:
1. The CPU reads the TDRE bit after it has been set to 1, then writes a 0 in this bit.
2. The data transfer controller (DTC) writes data in the TDR.
This bit is set to 1 at the following times:
(Initial value)
1. The chip is reset or enters a standby mode.
2. When TDR contents are transferred to the TSR.
3. When TDRE = 0 and the TE bit is cleared to 0.
Bit 6—Receive Data Register Full (RDRF): This bit indicates when one character has been
received and transferred to the RDR.
Bit 6
RDRF
0
1
Description
This bit is cleared from 1 to 0 when:
(Initial value)
1. The CPU reads the RDRF bit after it has been set to 1, then writes a 0 in this bit.
2. The data transfer controller (DTC) reads the RDR.
3. The chip is reset or enters a standby mode.
This bit is set to 1 when one character is received without error and transferred from the
RSR to the RDR.
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