HD6475348R Datasheet, PDF (239/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in the TCR, the
timer counter can be cleared when compare-match A or B occurs. Figure 11-5 shows the timing
of this operation.
ø
Internal
compare-match
signal
TCNT
N
H'00
Figure 11-5 Timing of Compare-Match Clear
11.3.3 External Reset of TCNT
When the CCLR1 and CCLR0 bits in the TCR are both set to 1, the timer counter is cleared on the
rising edge of an external reset input. Figure 11-6 shows the timing of this operation.
ø
External reset
input (TMRI)
Internal clear
pulse
TCNT
N–1
N
H'00
Figure 11-6 Timing of External Reset
223