HD6475348R Datasheet, PDF (127/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

5.4.2 Stack Status after Interrupt Handling Sequence
Figure 5-3 (a) and (b) show the stack before and after the interrupt exception-handling sequence.
Address
Address
2m – 4
2m – 3
2m – 2
2m – 1
2m
Stack area
2m – 4
Upper 8 bits of SR
SP
2m – 3
Lower 8 bits of SR
2m – 2
Upper 8 bits of PC
2m – 1
Lower 8 bits of PC
SP
2m
(Before)
Save to stack
Notes:
1. PC: The address of the next instruction to be executed is saved.
2. Register saving and restoring must start at an even address (e.g 2m).
(After)
Figure 5-3 (a) Stack before and after Interrupt Exception-Handling
(Minimum Mode)
Fig. 5-3(a)
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