HD6475348R Datasheet, PDF (118/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

5.1.3 Register Configuration
The six interrupt priority registers (IPRA to IPRF) and six data transfer enable registers (DTEA to
DTEF) are 8-bit registers located at addresses H'FF00 to H'FF0D in the register field in page 0 of
the address space. Table 5-1 lists their attributes.
Table 5-1 Interrupt Controller Registers
Name
Interrupt
A
priority
B
register
C
D
E
F
Data transfer A
enable
B
register
C
D
E
F
Abbreviation
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
DTEA
DTEB
DTEC
DTED
DTEE
DTEF
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
H'FF00
H'FF01
H'FF02
H'FF03
H'FF04
H'FF05
H'FF08
H'FF09
H'FF0A
H'FF0B
H'FF0C
H'FF0D
Initial Value
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
See section 6.2.5, “Data Transfer Enable Registers A to F” for further information about DTEA to
DTEF.
5.2 Interrupt Types
There are 30 distinct types of interrupts: 7 external interrupts originating off-chip and 23 internal
interrupts originating in the on-chip supporting modules.
5.2.1 External Interrupts
The seven external interrupts are NMI, IRQ0, and IRQ1 to IRQ5.
NMI (NonMaskable Interrupt): This interrupt has the highest priority level (8) and cannot be
masked. An NMI is generated by input to the NMI pin, and can also be generated by a watchdog
timer (WDT) overflow. The input at the NMI pin is edge-sensed. A user program can select
whether to have the interrupt occur on the rising edge or falling edge of the NMI input by setting
or clearing the nonmaskable interrupt edge bit (NMIEG) in system control register 1 (SYSCR1).
In the NMI exception-handling sequence, the T (Trace) bit in the CPU status register (SR) is
cleared to "0," and the interrupt mask level in I2 to I0 is set to 7, masking all other interrupts. The
interrupt controller holds the NMI request until the NMI exception-handling sequence begins,
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